ipa_data-v4.9.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (C) 2021-2024 Linaro Ltd. */
  3. #include <linux/array_size.h>
  4. #include <linux/log2.h>
  5. #include "../ipa_data.h"
  6. #include "../ipa_endpoint.h"
  7. #include "../ipa_mem.h"
  8. #include "../ipa_version.h"
  9. /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.9 */
  10. enum ipa_resource_type {
  11. /* Source resource types; first must have value 0 */
  12. IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
  13. IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
  14. IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
  15. IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
  16. IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
  17. /* Destination resource types; first must have value 0 */
  18. IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
  19. IPA_RESOURCE_TYPE_DST_DPS_DMARS,
  20. };
  21. /* Resource groups used for an SoC having IPA v4.9 */
  22. enum ipa_rsrc_group_id {
  23. /* Source resource group identifiers */
  24. IPA_RSRC_GROUP_SRC_UL_DL = 0,
  25. IPA_RSRC_GROUP_SRC_DMA,
  26. IPA_RSRC_GROUP_SRC_UC_RX_Q,
  27. IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
  28. /* Destination resource group identifiers */
  29. IPA_RSRC_GROUP_DST_UL_DL_DPL = 0,
  30. IPA_RSRC_GROUP_DST_DMA,
  31. IPA_RSRC_GROUP_DST_UC,
  32. IPA_RSRC_GROUP_DST_DRB_IP,
  33. IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
  34. };
  35. /* QSB configuration data for an SoC having IPA v4.9 */
  36. static const struct ipa_qsb_data ipa_qsb_data[] = {
  37. [IPA_QSB_MASTER_DDR] = {
  38. .max_writes = 8,
  39. .max_reads = 0, /* no limit (hardware max) */
  40. .max_reads_beats = 120,
  41. },
  42. };
  43. /* Endpoint configuration data for an SoC having IPA v4.9 */
  44. static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
  45. [IPA_ENDPOINT_AP_COMMAND_TX] = {
  46. .ee_id = GSI_EE_AP,
  47. .channel_id = 6,
  48. .endpoint_id = 7,
  49. .toward_ipa = true,
  50. .channel = {
  51. .tre_count = 256,
  52. .event_count = 256,
  53. .tlv_count = 20,
  54. },
  55. .endpoint = {
  56. .config = {
  57. .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
  58. .dma_mode = true,
  59. .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
  60. .tx = {
  61. .seq_type = IPA_SEQ_DMA,
  62. },
  63. },
  64. },
  65. },
  66. [IPA_ENDPOINT_AP_LAN_RX] = {
  67. .ee_id = GSI_EE_AP,
  68. .channel_id = 7,
  69. .endpoint_id = 11,
  70. .toward_ipa = false,
  71. .channel = {
  72. .tre_count = 256,
  73. .event_count = 256,
  74. .tlv_count = 9,
  75. },
  76. .endpoint = {
  77. .config = {
  78. .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
  79. .aggregation = true,
  80. .status_enable = true,
  81. .rx = {
  82. .buffer_size = 8192,
  83. .pad_align = ilog2(sizeof(u32)),
  84. .aggr_time_limit = 500,
  85. },
  86. },
  87. },
  88. },
  89. [IPA_ENDPOINT_AP_MODEM_TX] = {
  90. .ee_id = GSI_EE_AP,
  91. .channel_id = 2,
  92. .endpoint_id = 2,
  93. .toward_ipa = true,
  94. .channel = {
  95. .tre_count = 512,
  96. .event_count = 512,
  97. .tlv_count = 16,
  98. },
  99. .endpoint = {
  100. .filter_support = true,
  101. .config = {
  102. .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
  103. .checksum = true,
  104. .qmap = true,
  105. .status_enable = true,
  106. .tx = {
  107. .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
  108. .status_endpoint =
  109. IPA_ENDPOINT_MODEM_AP_RX,
  110. },
  111. },
  112. },
  113. },
  114. [IPA_ENDPOINT_AP_MODEM_RX] = {
  115. .ee_id = GSI_EE_AP,
  116. .channel_id = 12,
  117. .endpoint_id = 20,
  118. .toward_ipa = false,
  119. .channel = {
  120. .tre_count = 256,
  121. .event_count = 256,
  122. .tlv_count = 9,
  123. },
  124. .endpoint = {
  125. .config = {
  126. .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
  127. .checksum = true,
  128. .qmap = true,
  129. .aggregation = true,
  130. .rx = {
  131. .buffer_size = 8192,
  132. .aggr_time_limit = 500,
  133. .aggr_close_eof = true,
  134. },
  135. },
  136. },
  137. },
  138. [IPA_ENDPOINT_MODEM_AP_TX] = {
  139. .ee_id = GSI_EE_MODEM,
  140. .channel_id = 0,
  141. .endpoint_id = 5,
  142. .toward_ipa = true,
  143. .endpoint = {
  144. .filter_support = true,
  145. },
  146. },
  147. [IPA_ENDPOINT_MODEM_AP_RX] = {
  148. .ee_id = GSI_EE_MODEM,
  149. .channel_id = 7,
  150. .endpoint_id = 16,
  151. .toward_ipa = false,
  152. },
  153. [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
  154. .ee_id = GSI_EE_MODEM,
  155. .channel_id = 2,
  156. .endpoint_id = 8,
  157. .toward_ipa = true,
  158. .endpoint = {
  159. .filter_support = true,
  160. },
  161. },
  162. };
  163. /* Source resource configuration data for an SoC having IPA v4.9 */
  164. static const struct ipa_resource ipa_resource_src[] = {
  165. [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
  166. .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
  167. .min = 1, .max = 12,
  168. },
  169. .limits[IPA_RSRC_GROUP_SRC_DMA] = {
  170. .min = 1, .max = 1,
  171. },
  172. .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
  173. .min = 1, .max = 12,
  174. },
  175. },
  176. [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
  177. .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
  178. .min = 20, .max = 20,
  179. },
  180. .limits[IPA_RSRC_GROUP_SRC_DMA] = {
  181. .min = 2, .max = 2,
  182. },
  183. .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
  184. .min = 3, .max = 3,
  185. },
  186. },
  187. [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
  188. .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
  189. .min = 38, .max = 38,
  190. },
  191. .limits[IPA_RSRC_GROUP_SRC_DMA] = {
  192. .min = 4, .max = 4,
  193. },
  194. .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
  195. .min = 8, .max = 8,
  196. },
  197. },
  198. [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
  199. .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
  200. .min = 0, .max = 4,
  201. },
  202. .limits[IPA_RSRC_GROUP_SRC_DMA] = {
  203. .min = 0, .max = 4,
  204. },
  205. .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
  206. .min = 0, .max = 4,
  207. },
  208. },
  209. [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
  210. .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
  211. .min = 30, .max = 30,
  212. },
  213. .limits[IPA_RSRC_GROUP_SRC_DMA] = {
  214. .min = 8, .max = 8,
  215. },
  216. .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
  217. .min = 8, .max = 8,
  218. },
  219. },
  220. };
  221. /* Destination resource configuration data for an SoC having IPA v4.9 */
  222. static const struct ipa_resource ipa_resource_dst[] = {
  223. [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
  224. .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
  225. .min = 9, .max = 9,
  226. },
  227. .limits[IPA_RSRC_GROUP_DST_DMA] = {
  228. .min = 1, .max = 1,
  229. },
  230. .limits[IPA_RSRC_GROUP_DST_UC] = {
  231. .min = 1, .max = 1,
  232. },
  233. .limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
  234. .min = 39, .max = 39,
  235. },
  236. },
  237. [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
  238. .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
  239. .min = 2, .max = 3,
  240. },
  241. .limits[IPA_RSRC_GROUP_DST_DMA] = {
  242. .min = 1, .max = 2,
  243. },
  244. .limits[IPA_RSRC_GROUP_DST_UC] = {
  245. .min = 0, .max = 2,
  246. },
  247. },
  248. };
  249. /* Resource configuration data for an SoC having IPA v4.9 */
  250. static const struct ipa_resource_data ipa_resource_data = {
  251. .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
  252. .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
  253. .resource_src_count = ARRAY_SIZE(ipa_resource_src),
  254. .resource_src = ipa_resource_src,
  255. .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
  256. .resource_dst = ipa_resource_dst,
  257. };
  258. /* IPA-resident memory region data for an SoC having IPA v4.9 */
  259. static const struct ipa_mem ipa_mem_local_data[] = {
  260. {
  261. .id = IPA_MEM_UC_SHARED,
  262. .offset = 0x0000,
  263. .size = 0x0080,
  264. .canary_count = 0,
  265. },
  266. {
  267. .id = IPA_MEM_UC_INFO,
  268. .offset = 0x0080,
  269. .size = 0x0200,
  270. .canary_count = 0,
  271. },
  272. {
  273. .id = IPA_MEM_V4_FILTER_HASHED,
  274. .offset = 0x0288,
  275. .size = 0x0078,
  276. .canary_count = 2,
  277. },
  278. {
  279. .id = IPA_MEM_V4_FILTER,
  280. .offset = 0x0308,
  281. .size = 0x0078,
  282. .canary_count = 2,
  283. },
  284. {
  285. .id = IPA_MEM_V6_FILTER_HASHED,
  286. .offset = 0x0388,
  287. .size = 0x0078,
  288. .canary_count = 2,
  289. },
  290. {
  291. .id = IPA_MEM_V6_FILTER,
  292. .offset = 0x0408,
  293. .size = 0x0078,
  294. .canary_count = 2,
  295. },
  296. {
  297. .id = IPA_MEM_V4_ROUTE_HASHED,
  298. .offset = 0x0488,
  299. .size = 0x0078,
  300. .canary_count = 2,
  301. },
  302. {
  303. .id = IPA_MEM_V4_ROUTE,
  304. .offset = 0x0508,
  305. .size = 0x0078,
  306. .canary_count = 2,
  307. },
  308. {
  309. .id = IPA_MEM_V6_ROUTE_HASHED,
  310. .offset = 0x0588,
  311. .size = 0x0078,
  312. .canary_count = 2,
  313. },
  314. {
  315. .id = IPA_MEM_V6_ROUTE,
  316. .offset = 0x0608,
  317. .size = 0x0078,
  318. .canary_count = 2,
  319. },
  320. {
  321. .id = IPA_MEM_MODEM_HEADER,
  322. .offset = 0x0688,
  323. .size = 0x0240,
  324. .canary_count = 2,
  325. },
  326. {
  327. .id = IPA_MEM_AP_HEADER,
  328. .offset = 0x08c8,
  329. .size = 0x0200,
  330. .canary_count = 0,
  331. },
  332. {
  333. .id = IPA_MEM_MODEM_PROC_CTX,
  334. .offset = 0x0ad0,
  335. .size = 0x0b20,
  336. .canary_count = 2,
  337. },
  338. {
  339. .id = IPA_MEM_AP_PROC_CTX,
  340. .offset = 0x15f0,
  341. .size = 0x0200,
  342. .canary_count = 0,
  343. },
  344. {
  345. .id = IPA_MEM_NAT_TABLE,
  346. .offset = 0x1800,
  347. .size = 0x0d00,
  348. .canary_count = 4,
  349. },
  350. {
  351. .id = IPA_MEM_STATS_QUOTA_MODEM,
  352. .offset = 0x2510,
  353. .size = 0x0030,
  354. .canary_count = 4,
  355. },
  356. {
  357. .id = IPA_MEM_STATS_QUOTA_AP,
  358. .offset = 0x2540,
  359. .size = 0x0048,
  360. .canary_count = 0,
  361. },
  362. {
  363. .id = IPA_MEM_STATS_TETHERING,
  364. .offset = 0x2588,
  365. .size = 0x0238,
  366. .canary_count = 0,
  367. },
  368. {
  369. .id = IPA_MEM_STATS_FILTER_ROUTE,
  370. .offset = 0x27c0,
  371. .size = 0x0800,
  372. .canary_count = 0,
  373. },
  374. {
  375. .id = IPA_MEM_STATS_DROP,
  376. .offset = 0x2fc0,
  377. .size = 0x0020,
  378. .canary_count = 0,
  379. },
  380. {
  381. .id = IPA_MEM_MODEM,
  382. .offset = 0x2fe8,
  383. .size = 0x0800,
  384. .canary_count = 2,
  385. },
  386. {
  387. .id = IPA_MEM_UC_EVENT_RING,
  388. .offset = 0x3800,
  389. .size = 0x1000,
  390. .canary_count = 1,
  391. },
  392. {
  393. .id = IPA_MEM_PDN_CONFIG,
  394. .offset = 0x4800,
  395. .size = 0x0050,
  396. .canary_count = 0,
  397. },
  398. };
  399. /* Memory configuration data for an SoC having IPA v4.9 */
  400. static const struct ipa_mem_data ipa_mem_data = {
  401. .local_count = ARRAY_SIZE(ipa_mem_local_data),
  402. .local = ipa_mem_local_data,
  403. .imem_addr = 0x146bd000,
  404. .imem_size = 0x00002000,
  405. .smem_id = 497,
  406. .smem_size = 0x00009000,
  407. };
  408. /* Interconnect rates are in 1000 byte/second units */
  409. static const struct ipa_interconnect_data ipa_interconnect_data[] = {
  410. {
  411. .name = "memory",
  412. .peak_bandwidth = 600000, /* 600 MBps */
  413. .average_bandwidth = 150000, /* 150 MBps */
  414. },
  415. /* Average rate is unused for the next interconnect */
  416. {
  417. .name = "config",
  418. .peak_bandwidth = 74000, /* 74 MBps */
  419. .average_bandwidth = 0, /* unused */
  420. },
  421. };
  422. /* Clock and interconnect configuration data for an SoC having IPA v4.9 */
  423. static const struct ipa_power_data ipa_power_data = {
  424. .core_clock_rate = 60 * 1000 * 1000, /* Hz */
  425. .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
  426. .interconnect_data = ipa_interconnect_data,
  427. };
  428. /* Configuration data for an SoC having IPA v4.9. */
  429. const struct ipa_data ipa_data_v4_9 = {
  430. .version = IPA_VERSION_4_9,
  431. .qsb_count = ARRAY_SIZE(ipa_qsb_data),
  432. .qsb_data = ipa_qsb_data,
  433. .modem_route_count = 8,
  434. .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
  435. .endpoint_data = ipa_gsi_endpoint_data,
  436. .resource_data = &ipa_resource_data,
  437. .mem_data = &ipa_mem_data,
  438. .power_data = &ipa_power_data,
  439. };