ipi-mux.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Multiplex several virtual IPIs over a single HW IPI.
  4. *
  5. * Copyright The Asahi Linux Contributors
  6. * Copyright (c) 2022 Ventana Micro Systems Inc.
  7. */
  8. #define pr_fmt(fmt) "ipi-mux: " fmt
  9. #include <linux/cpu.h>
  10. #include <linux/init.h>
  11. #include <linux/irq.h>
  12. #include <linux/irqchip.h>
  13. #include <linux/irqchip/chained_irq.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/jump_label.h>
  16. #include <linux/percpu.h>
  17. #include <linux/smp.h>
  18. struct ipi_mux_cpu {
  19. atomic_t enable;
  20. atomic_t bits;
  21. };
  22. static struct ipi_mux_cpu __percpu *ipi_mux_pcpu;
  23. static struct irq_domain *ipi_mux_domain;
  24. static void (*ipi_mux_send)(unsigned int cpu);
  25. static void ipi_mux_mask(struct irq_data *d)
  26. {
  27. struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
  28. atomic_andnot(BIT(irqd_to_hwirq(d)), &icpu->enable);
  29. }
  30. static void ipi_mux_unmask(struct irq_data *d)
  31. {
  32. struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
  33. u32 ibit = BIT(irqd_to_hwirq(d));
  34. atomic_or(ibit, &icpu->enable);
  35. /*
  36. * The atomic_or() above must complete before the atomic_read()
  37. * below to avoid racing ipi_mux_send_mask().
  38. */
  39. smp_mb__after_atomic();
  40. /* If a pending IPI was unmasked, raise a parent IPI immediately. */
  41. if (atomic_read(&icpu->bits) & ibit)
  42. ipi_mux_send(smp_processor_id());
  43. }
  44. static void ipi_mux_send_mask(struct irq_data *d, const struct cpumask *mask)
  45. {
  46. struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
  47. u32 ibit = BIT(irqd_to_hwirq(d));
  48. unsigned long pending;
  49. int cpu;
  50. for_each_cpu(cpu, mask) {
  51. icpu = per_cpu_ptr(ipi_mux_pcpu, cpu);
  52. /*
  53. * This sequence is the mirror of the one in ipi_mux_unmask();
  54. * see the comment there. Additionally, release semantics
  55. * ensure that the vIPI flag set is ordered after any shared
  56. * memory accesses that precede it. This therefore also pairs
  57. * with the atomic_fetch_andnot in ipi_mux_process().
  58. */
  59. pending = atomic_fetch_or_release(ibit, &icpu->bits);
  60. /*
  61. * The atomic_fetch_or_release() above must complete
  62. * before the atomic_read() below to avoid racing with
  63. * ipi_mux_unmask().
  64. */
  65. smp_mb__after_atomic();
  66. /*
  67. * The flag writes must complete before the physical IPI is
  68. * issued to another CPU. This is implied by the control
  69. * dependency on the result of atomic_read() below, which is
  70. * itself already ordered after the vIPI flag write.
  71. */
  72. if (!(pending & ibit) && (atomic_read(&icpu->enable) & ibit))
  73. ipi_mux_send(cpu);
  74. }
  75. }
  76. static const struct irq_chip ipi_mux_chip = {
  77. .name = "IPI Mux",
  78. .irq_mask = ipi_mux_mask,
  79. .irq_unmask = ipi_mux_unmask,
  80. .ipi_send_mask = ipi_mux_send_mask,
  81. };
  82. static int ipi_mux_domain_alloc(struct irq_domain *d, unsigned int virq,
  83. unsigned int nr_irqs, void *arg)
  84. {
  85. int i;
  86. for (i = 0; i < nr_irqs; i++) {
  87. irq_set_percpu_devid(virq + i);
  88. irq_domain_set_info(d, virq + i, i, &ipi_mux_chip, NULL,
  89. handle_percpu_devid_irq, NULL, NULL);
  90. }
  91. return 0;
  92. }
  93. static const struct irq_domain_ops ipi_mux_domain_ops = {
  94. .alloc = ipi_mux_domain_alloc,
  95. .free = irq_domain_free_irqs_top,
  96. };
  97. /**
  98. * ipi_mux_process - Process multiplexed virtual IPIs
  99. */
  100. void ipi_mux_process(void)
  101. {
  102. struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
  103. irq_hw_number_t hwirq;
  104. unsigned long ipis;
  105. unsigned int en;
  106. /*
  107. * Reading enable mask does not need to be ordered as long as
  108. * this function is called from interrupt handler because only
  109. * the CPU itself can change it's own enable mask.
  110. */
  111. en = atomic_read(&icpu->enable);
  112. /*
  113. * Clear the IPIs we are about to handle. This pairs with the
  114. * atomic_fetch_or_release() in ipi_mux_send_mask().
  115. */
  116. ipis = atomic_fetch_andnot(en, &icpu->bits) & en;
  117. for_each_set_bit(hwirq, &ipis, BITS_PER_TYPE(int))
  118. generic_handle_domain_irq(ipi_mux_domain, hwirq);
  119. }
  120. /**
  121. * ipi_mux_create - Create virtual IPIs multiplexed on top of a single
  122. * parent IPI.
  123. * @nr_ipi: number of virtual IPIs to create. This should
  124. * be <= BITS_PER_TYPE(int)
  125. * @mux_send: callback to trigger parent IPI for a particular CPU
  126. *
  127. * Returns first virq of the newly created virtual IPIs upon success
  128. * or <=0 upon failure
  129. */
  130. int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu))
  131. {
  132. struct fwnode_handle *fwnode;
  133. struct irq_domain *domain;
  134. int rc;
  135. if (ipi_mux_domain)
  136. return -EEXIST;
  137. if (BITS_PER_TYPE(int) < nr_ipi || !mux_send)
  138. return -EINVAL;
  139. ipi_mux_pcpu = alloc_percpu(typeof(*ipi_mux_pcpu));
  140. if (!ipi_mux_pcpu)
  141. return -ENOMEM;
  142. fwnode = irq_domain_alloc_named_fwnode("IPI-Mux");
  143. if (!fwnode) {
  144. pr_err("unable to create IPI Mux fwnode\n");
  145. rc = -ENOMEM;
  146. goto fail_free_cpu;
  147. }
  148. domain = irq_domain_create_linear(fwnode, nr_ipi,
  149. &ipi_mux_domain_ops, NULL);
  150. if (!domain) {
  151. pr_err("unable to add IPI Mux domain\n");
  152. rc = -ENOMEM;
  153. goto fail_free_fwnode;
  154. }
  155. domain->flags |= IRQ_DOMAIN_FLAG_IPI_SINGLE;
  156. irq_domain_update_bus_token(domain, DOMAIN_BUS_IPI);
  157. rc = irq_domain_alloc_irqs(domain, nr_ipi, NUMA_NO_NODE, NULL);
  158. if (rc <= 0) {
  159. pr_err("unable to alloc IRQs from IPI Mux domain\n");
  160. goto fail_free_domain;
  161. }
  162. ipi_mux_domain = domain;
  163. ipi_mux_send = mux_send;
  164. return rc;
  165. fail_free_domain:
  166. irq_domain_remove(domain);
  167. fail_free_fwnode:
  168. irq_domain_free_fwnode(fwnode);
  169. fail_free_cpu:
  170. free_percpu(ipi_mux_pcpu);
  171. return rc;
  172. }