ark1668ed-bsp/u-boot/arch/arm/mach-arkmicro/ddr_ark1668ed.c

#include <common.h>
#include <linux/delay.h>
#include <asm/arch/ark1668ed-sysreg.h>

#define REGS_DDRCTL_BASE				0x51400000
#define REGS_DDRPHY_BASE				0x51500000


#define DDRPLL_CLK  400

#define	ApbReadFun(base)			*(volatile unsigned int *)(base)
#define DDR_CLK  (DDRPLL_CLK * 2)
#define n_clk (DDRPLL_CLK)

#define	CWL								8
#define	CAS_Latency						11//10
#define	MR2_CWL								MCTL_MR2_CWL_8
#define	MR0_CL								MCTL_MR0_CAS_Latency_11
#define	AL_0								1
#define	AL								0

// MR0 (Mode Register 0)
#define MCTL_MR0_BL_8_Fixed				(0 << 0)		// 8 (Fixed)
#define MCTL_MR0_BL_ON_THE_FLY			(1 << 0)		// BC4 or 8 (on the fly)
#define MCTL_MR0_BL_BC4_Fixed			(2 << 0)		// BC4 (Fixed)
#define MCTL_MR0_CL						(1 << 2)
#define MCTL_MR0_RBT_Nibble_Sequential	(0 << 3)
#define MCTL_MR0_RBT_Interleave			(1 << 3)
#define MCTL_MR0_CAS_Latency_5			(1 << 4)
#define MCTL_MR0_CAS_Latency_6			(2 << 4)
#define MCTL_MR0_CAS_Latency_7			(3 << 4)
#define MCTL_MR0_CAS_Latency_8			(4 << 4)
#define MCTL_MR0_CAS_Latency_9			(5 << 4)
#define MCTL_MR0_CAS_Latency_10			(6 << 4)
#define MCTL_MR0_CAS_Latency_11			(7 << 4)
#define MCTL_MR0_CAS_Latency_12			(1 << 2)
#define MCTL_MR0_CAS_Latency_13			((1 << 2) | (1 << 4))
#define MCTL_MR0_CAS_Latency_14			((1 << 2) | (1 << 5))
#define MCTL_MR0_CAS_Latency_15			((1 << 2) | (1 << 4) | (1 << 5))
#define MCTL_MR0_CAS_Latency_16			((1 << 2) | (1 << 6))

#define MCTL_MR0_TM_Normal				(0 << 7)
#define MCTL_MR0_TM_Test				(1 << 7)
//DLL Reset
//The DLL Reset bit is self-clearing, meaning that it returns back to the value of ??0?ˉ after the DLL reset function
//has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any time that
//the DLL reset function is used, tDLLK must be met before any functions that require the DLL can be used
#define MCTL_MR0_DLL_Reset_No			(0 << 8)
#define MCTL_MR0_DLL_Reset_Yes			(1 << 8)
#define MCTL_MR0_WR_16					(0)
#define MCTL_MR0_WR_5					(1)
#define MCTL_MR0_WR_6					(2)
#define MCTL_MR0_WR_7					(3)
#define MCTL_MR0_WR_8					(4)
#define MCTL_MR0_WR_10					(5)
#define MCTL_MR0_WR_12					(6)
#define MCTL_MR0_WR_14					(7)
#define MCTL_MR0_WR(cycle)				(((cycle)&0x07) << 9)	 // Write recovery for autoprecharge
// DLL Control for Precharge PD
#define MCTL_MR0_PPD_Slow_exit			(0 << 12)		// Slow exit (DLL off)
#define MCTL_MR0_PPD_Fast_exit			(1 << 12)		// Fast exit (DLL on)
#define MCTL_MR0_PPD_MASK				(1 << 12)
// MR1 (Mode Register 1)
#define MCTL_MR1_DLL_Enable				(0 << 0)			// 0 Enable
#define MCTL_MR1_DLL_Disable			(1 << 0)			// 1 Disable
// A5 A1 Output Driver Impedance Control	(RZQ = 240 |?)
#define MCTL_MR1_DIC_RZQ_6				((0 << 1) | (0 << 5))
#define MCTL_MR1_DIC_RZQ_7				((1 << 1) | (0 << 5))
#define MCTL_MR1_Rtt_Nom_disabled		((0 << 9) | (0 << 6) | (0 << 2))
#define MCTL_MR1_Rtt_Nom_RZQ_4			((0 << 9) | (0 << 6) | (1 << 2))
#define MCTL_MR1_Rtt_Nom_RZQ_2			((0 << 9) | (1 << 6) | (0 << 2))
#define MCTL_MR1_Rtt_Nom_RZQ_6			((0 << 9) | (1 << 6) | (1 << 2))
#define MCTL_MR1_Rtt_Nom_RZQ_12			((1 << 9) | (0 << 6) | (0 << 2))
#define MCTL_MR1_Rtt_Nom_RZQ_8			((1 << 9) | (0 << 6) | (1 << 2))
#define MCTL_MR1_AL_0_disabled			(0 << 3)
#define MCTL_MR1_AL_CL_1				(1 << 3)
#define MCTL_MR1_AL_CL_2				(2 << 3)

#define MCTL_MR1_Write_leveling_Disabled		(0 << 7)
#define MCTL_MR1_Write_leveling_Enabled			(1 << 7)
//#define MCTL_MR1_TDQS_Disabled				(0 << 11)
//#define MCTL_MR1_TDQS_Enabled					(1 << 11)
#define MCTL_MR1_Qoff_Output_buffer_enabled		(0 << 12)
#define MCTL_MR1_Qoff_Output_buffer_disabled	(1 << 12)		// Outputs disabled - DQs, DQSs, DQS#s.

// MR2 (Mode Register 2)
// A5 A4 A3 CAS write Latency (CWL)
#define MCTL_MR2_CWL_5					(0 << 3)			// 5 (tCK(avg) ?Y 2.5ns)
#define MCTL_MR2_CWL_6					(1 << 3)			// 6 (2.5ns > tCK(avg) ?Y 1.875ns)
#define MCTL_MR2_CWL_7					(2 << 3)			// 7 (1.875ns > tCK(avg) ?Y 1.5ns)
#define MCTL_MR2_CWL_8					(3 << 3)			// 8 (1.5ns > tCK(avg) ?Y 1.25ns)
#define MCTL_MR2_CWL_9					(4 << 3)			// 9 (1.25ns > tCK(avg) ?Y 1.07ns)
#define MCTL_MR2_CWL_10					(5 << 3)			// 9 (1.07ns > tCK(avg) ?Y 0.935ns)

// A6 Auto Self-Refresh (ASR)
#define MCTL_MR2_ASR_SRT				(0 << 6)			// 0 Manual SR Reference (SRT)
#define MCTL_MR2_ASR_enable				(1 << 6)			// 1 ASR enable (Optional)
// A7 Self-Refresh Temperature (SRT) Range
#define MCTL_MR2_SRT_Normal_range		(0 << 7)			// 0 Normal operating temperature range
#define MCTL_MR2_SRT_Extended_range		(1 << 7)			// 1 Extended (optional) operating temperature range
// A10 A9 Rtt_WR *2
#define MCTL_MR2_Rtt_WR_Dynamic_ODT_off	(0 << 9)			// 0 0 Dynamic ODT off (Write does not affect Rtt value)
#define MCTL_MR2_Rtt_WR_RZQ_4			(1 << 9)			// 0 1 RZQ/4
#define MCTL_MR2_Rtt_WR_RZQ_2			(2 << 9)			// 1 0 RZQ/2

// Multi purpose registers
// MR3 (Mode Register MR3)
#define MCTL_MR3_MPR_location_Predefined pattern(0 << 0)
#define MCTL_MR3_MPR_Normal_operation				(0 << 2)
#define MCTL_MR3_MPR_Dataflow_from_MPR				(1 << 2)



#define	DDR_CALC(time)					(unsigned int)((((time) * (DDR_CLK) * 105  + 1000*100 - 1) / (1000*100))+1)
#define	DDR_CALC_EXACT_VALUE(time)		(unsigned int)(((time) * (n_clk) * 100  + 1000*100 - 1) / (1000*100))

#define RAFB32(n)						(~(0xffffffff << n))
#define LAFB32(n)						(~(0xffffffff >> n))

#define ddrs_mstr_addr					(REGS_DDRCTL_BASE + 0x00000000)
#define ddrs_stat_addr					(REGS_DDRCTL_BASE + 0x00000004)
#define ddrs_mrctrl0_addr				(REGS_DDRCTL_BASE + 0x00000010)
#define ddrs_mrctrl1_addr				(REGS_DDRCTL_BASE + 0x00000014)
#define ddrs_pwrctl_addr				(REGS_DDRCTL_BASE + 0x00000030)
#define ddrs_hwlpctl_addr				(REGS_DDRCTL_BASE + 0x00000038)
#define ddrs_rfshctl3_addr				(REGS_DDRCTL_BASE + 0x00000060)
#define ddrs_rfshtmg_addr				(REGS_DDRCTL_BASE + 0x00000064)
#define ddrs_init0_addr					(REGS_DDRCTL_BASE + 0x000000d0)
#define ddrs_init1_addr					(REGS_DDRCTL_BASE + 0x000000d4)
#define ddrs_init2_addr					(REGS_DDRCTL_BASE + 0x000000d8)
#define ddrs_init3_addr					(REGS_DDRCTL_BASE + 0x000000dc)
#define ddrs_init4_addr					(REGS_DDRCTL_BASE + 0x000000e0)
#define ddrs_zqctl_addr					(REGS_DDRCTL_BASE + 0x00000180)
#define ddrs_dfitmg0_addr				(REGS_DDRCTL_BASE + 0x00000190)
#define ddrs_dfitmg1_addr				(REGS_DDRCTL_BASE + 0x00000194)
#define ddrs_dfimisc_addr				(REGS_DDRCTL_BASE + 0x000001b0)
#define ddrs_dbg1_addr					(REGS_DDRCTL_BASE + 0x00000304)
#define ddrs_dbgcam_addr				(REGS_DDRCTL_BASE + 0x00000308)
#define ddrs_swstat_addr				(REGS_DDRCTL_BASE + 0x00000324)
#define ddrs_swctlstatic_addr			(REGS_DDRCTL_BASE + 0x00000328)
#define ddrs_swctl_addr					(REGS_DDRCTL_BASE + 0x00000320)

#define ddrs_pcfg_0_addr				(REGS_DDRCTL_BASE + 0x00000404 + 0x00000000)
#define ddrs_pcfg_1_addr				(REGS_DDRCTL_BASE + 0x00000404 + 0x000000b0)
#define ddrs_pcfg_2_addr				(REGS_DDRCTL_BASE + 0x00000404 + 0x00000160)
#define ddrs_pcfg_3_addr				(REGS_DDRCTL_BASE + 0x00000404 + 0x00000210)
#define ddrs_pcfg_w0_addr				(REGS_DDRCTL_BASE + 0x00000408 + 0x00000000)
#define ddrs_pcfg_w1_addr				(REGS_DDRCTL_BASE + 0x00000408 + 0x000000b0)
#define ddrs_pcfg_w2_addr				(REGS_DDRCTL_BASE + 0x00000408 + 0x00000160)
#define ddrs_pcfg_w3_addr				(REGS_DDRCTL_BASE + 0x00000408 + 0x00000210)
#define ddrs_pctrl_0_addr				(REGS_DDRCTL_BASE + 0x00000490 + 0x00000000)
#define ddrs_pctrl_1_addr				(REGS_DDRCTL_BASE + 0x00000490 + 0x000000b0)
#define ddrs_pctrl_2_addr				(REGS_DDRCTL_BASE + 0x00000490 + 0x00000160)
#define ddrs_pctrl_3_addr				(REGS_DDRCTL_BASE + 0x00000490 + 0x00000210)
#define ddrs_pcfgrqos0_0_addr			(REGS_DDRCTL_BASE + 0x00000494 + 0x00000000)
#define ddrs_pcfgrqos0_1_addr			(REGS_DDRCTL_BASE + 0x00000494 + 0x000000b0)
#define ddrs_pcfgrqos0_2_addr			(REGS_DDRCTL_BASE + 0x00000494 + 0x00000160)
#define ddrs_pcfgrqos0_3_addr			(REGS_DDRCTL_BASE + 0x00000494 + 0x00000210)
#define ddrs_pcfgrqos1_0_addr			(REGS_DDRCTL_BASE + 0x00000498 + 0x00000000)
#define ddrs_pcfgrqos1_1_addr			(REGS_DDRCTL_BASE + 0x00000498 + 0x000000b0)
#define ddrs_pcfgrqos1_2_addr			(REGS_DDRCTL_BASE + 0x00000498 + 0x00000160)
#define ddrs_pcfgrqos1_3_addr			(REGS_DDRCTL_BASE + 0x00000498 + 0x00000210)
#define ddrs_pcfgwqos0_0_addr			(REGS_DDRCTL_BASE + 0x0000049c + 0x00000000)
#define ddrs_pcfgwqos0_1_addr			(REGS_DDRCTL_BASE + 0x0000049c + 0x000000b0)
#define ddrs_pcfgwqos0_2_addr			(REGS_DDRCTL_BASE + 0x0000049c + 0x00000160)
#define ddrs_pcfgwqos0_3_addr			(REGS_DDRCTL_BASE + 0x0000049c + 0x00000210)
#define ddrs_pcfgwqos1_0_addr			(REGS_DDRCTL_BASE + 0x000004a0 + 0x00000000)
#define ddrs_pcfgwqos1_1_addr			(REGS_DDRCTL_BASE + 0x000004a0 + 0x000000b0)
#define ddrs_pcfgwqos1_2_addr			(REGS_DDRCTL_BASE + 0x000004a0 + 0x00000160)
#define ddrs_pcfgwqos1_3_addr			(REGS_DDRCTL_BASE + 0x000004a0 + 0x00000210)
#define ddrs_dramtmg0_addr				(REGS_DDRCTL_BASE + 0x00000100)
#define ddrs_dramtmg1_addr				(REGS_DDRCTL_BASE + 0x00000104)
#define ddrs_dramtmg2_addr				(REGS_DDRCTL_BASE + 0x00000108)
#define ddrs_dramtmg3_addr				(REGS_DDRCTL_BASE + 0x0000010c)
#define ddrs_dramtmg4_addr				(REGS_DDRCTL_BASE + 0x00000110)
#define ddrs_dramtmg5_addr				(REGS_DDRCTL_BASE + 0x00000114)
#define ddrs_dramtmg8_addr				(REGS_DDRCTL_BASE + 0x00000120)
#define ddrs_addrmap0_addr				(REGS_DDRCTL_BASE + 0x00000200)
#define ddrs_addrmap1_addr				(REGS_DDRCTL_BASE + 0x00000204)
#define ddrs_addrmap2_addr				(REGS_DDRCTL_BASE + 0x00000208)
#define ddrs_addrmap3_addr				(REGS_DDRCTL_BASE + 0x0000020c)
#define ddrs_addrmap4_addr				(REGS_DDRCTL_BASE + 0x00000210)
#define ddrs_addrmap5_addr				(REGS_DDRCTL_BASE + 0x00000214)
#define ddrs_addrmap6_addr				(REGS_DDRCTL_BASE + 0x00000218)
#define ddrs_addrmap7_addr				(REGS_DDRCTL_BASE + 0x0000021c)
#define ddrs_addrmap8_addr				(REGS_DDRCTL_BASE + 0x00000220)
#define ddrs_addrmap9_addr				(REGS_DDRCTL_BASE + 0x00000224)
#define ddrs_addrmap10_addr				(REGS_DDRCTL_BASE + 0x00000228)
#define ddrs_addrmap11_addr				(REGS_DDRCTL_BASE + 0x0000022c)
#define ddrs_odtcfg_addr				(REGS_DDRCTL_BASE + 0x00000240)
#define ddrs_sched_addr					(REGS_DDRCTL_BASE + 0x00000250)
#define ddrs_sched1_addr				(REGS_DDRCTL_BASE + 0x00000254)
#define ddrs_per1_addr					(REGS_DDRCTL_BASE + 0x0000025c)
#define ddrs_per2_addr					(REGS_DDRCTL_BASE + 0x00000264)
#define ddrs_per3_addr					(REGS_DDRCTL_BASE + 0x0000026c)

#define ddrsphy_pir_addr				(REGS_DDRPHY_BASE + (0x00000001 << 2))
#define ddrsphy_pgsr0_addr				(REGS_DDRPHY_BASE + (0x00000004 << 2))
#define ddrsphy_pllcr_addr				(REGS_DDRPHY_BASE + (0x00000006 << 2))
#define ddrsphy_ptr0_addr				(REGS_DDRPHY_BASE + (0x00000007 << 2))
#define ddrsphy_ptr1_addr				(REGS_DDRPHY_BASE + (0x00000008 << 2))
#define ddrsphy_ptr2_addr				(REGS_DDRPHY_BASE + (0x00000009 << 2))
#define ddrsphy_ptr3_addr				(REGS_DDRPHY_BASE + (0x0000000a << 2))
#define ddrsphy_ptr4_addr				(REGS_DDRPHY_BASE + (0x0000000b << 2))

#define ddrsphy_dxccr_addr				(REGS_DDRPHY_BASE + (0x0000000f << 2))

#define ddrsphy_dsgcr_addr				(REGS_DDRPHY_BASE + (0x00000010 << 2))
#define ddrsphy_dcr_addr				(REGS_DDRPHY_BASE + (0x00000011 << 2))
#define ddrsphy_dtpr0_addr				(REGS_DDRPHY_BASE + (0x00000012 << 2))
#define ddrsphy_dtpr1_addr				(REGS_DDRPHY_BASE + (0x00000013 << 2))

#define ddrsphy_dtpr2_addr				(REGS_DDRPHY_BASE + (0x00000014 << 2))
#define ddrsphy_mr0_addr				(REGS_DDRPHY_BASE + (0x00000015 << 2))
#define ddrsphy_mr1_addr				(REGS_DDRPHY_BASE + (0x00000016 << 2))
#define ddrsphy_mr2_addr				(REGS_DDRPHY_BASE + (0x00000017 << 2))
#define ddrsphy_mr3_addr				(REGS_DDRPHY_BASE + (0x00000018 << 2))
#define ddrsphy_dtcr_addr				(REGS_DDRPHY_BASE + (0x0000001a << 2))
#define ddrsphy_pgcr2_addr				(REGS_DDRPHY_BASE + (0x00000023 << 2))

#define ddrsphy_zq0cr0_addr				(REGS_DDRPHY_BASE + (0x00000060 << 2))
#define ddrsphy_zq0cr1_addr				(REGS_DDRPHY_BASE + (0x00000061 << 2))
#define ddrsphy_zq0sr0_addr				(REGS_DDRPHY_BASE + (0x00000062 << 2))
#define ddrsphy_zq0sr1_addr				(REGS_DDRPHY_BASE + (0x00000063 << 2))


static void ApbWriteFun(unsigned int addr, unsigned int data)
{
	* (volatile unsigned int *) addr = data;
}

static void ApbWriteFun_qussi(unsigned int addr, unsigned int data)
{
	ApbWriteFun(ddrs_swctl_addr, 0x0);
	*(volatile unsigned int *) addr = data;
	ApbWriteFun(ddrs_swctl_addr, 0x1);
}

void ddr_init(void)
{
	uint32_t rdata, tmp;
	uint32_t rval;
	uint32_t val = 0;
	int mrdata;
	unsigned int WR;

	(void)val;
	//int loop;
	//ddr param based on ddr clk cycles
	unsigned int WL = CWL + AL;
	unsigned int RL = CAS_Latency + AL;			//The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL + CL.
	unsigned int tRCD = CAS_Latency;
	unsigned int TRAS = DDR_CALC(36);			// OK, Activate to precharge command delay,
	unsigned int TRC = tRCD + TRAS;				// OK
	unsigned int tRRD = max(4u, DDR_CALC(7.5));	// tRRD = max(4tCK,7.5ns)
	unsigned int TRTP = max(4u, DDR_CALC(7.5));	// OK, Internal read to precharge command delay.
	unsigned int tWTR = max(4u, DDR_CALC(7.5));
	unsigned int tRP = CAS_Latency;				// NG
	unsigned int tMRD = 4;						// tMRD 4 - 4 - nCK
	unsigned int TMOD = max(12u, DDR_CALC(15));	// DDR3 Legal Values: 0..31
	unsigned int TXP = max(3u, DDR_CALC(6));

	//unsigned int tRFC = DDR_CALC(110);
	unsigned int tCKSRX = max(5u, DDR_CALC(10));

	WR = DDR_CALC(15);
	//controller param, based on DFI clk cycles
	unsigned int wr2pre = (WL + 4 + WR + 1) / 2;
	unsigned int tfaw = DDR_CALC_EXACT_VALUE(40);
	unsigned int tras_min = DDR_CALC_EXACT_VALUE(36);
	unsigned int tras_max = 11;	//11; // 9*trefi/1024
	unsigned int txp = 3;		// 6ns
	unsigned int trtp = (TRTP + 1) / 2;
	unsigned int trc = 20;		// DDR_CALC_EXACT_VALUE(46);
	unsigned int twtr = 8;		// 7.5ns
	unsigned int tCKE = (max(3u, DDR_CALC(5)) + 1) / 2;
	unsigned int tXS =  DDR_CALC_EXACT_VALUE(110+10)/32;
//	unsigned int twr2pre = 15;
	int retries = 10;
	int timeout;

restart:
	if (WR < 6)
		WR = 6;
	else if (WR == 9)
		WR = 10;
	else if (WR == 11)
		WR = 12;
	else if (WR == 13)
		WR = 14;
	else if (WR == 15)
		WR = 16;

#if 1
	ApbWriteFun_qussi(ddrs_pctrl_0_addr, 0x1);
	ApbWriteFun_qussi(ddrs_pctrl_1_addr, 0x1);
	ApbWriteFun_qussi(ddrs_pctrl_2_addr, 0x1);
	ApbWriteFun_qussi(ddrs_pctrl_3_addr, 0x1);

	rval = rSYS_SOFTRESET_CTL1;
	rval &= ~(0x3f << 16);
	rSYS_SOFTRESET_CTL1 = rval;
	udelay(1000);
	rval |= 0x3f << 16;
	rSYS_SOFTRESET_CTL1 = rval;
	udelay(1000);
#endif

//	Controller Initialization
	rval = readl(ddrs_mstr_addr);
	rval |= (1 << 10) | (1 << 0);
	writel(rval, ddrs_mstr_addr);

	// init ddr
	// step 1-3
	//Enables static register programming outside reset
	ApbWriteFun(ddrs_swctlstatic_addr, 0x1);


	//24:16 dram_rstn_x1024
	//For use with a Synopsys DDR PHY, this must be set to a minimum of 1.
	//ApbWriteFun(ddrs_init1_addr, 0x0001000f);
	ApbWriteFun(ddrs_init1_addr, 0x00010001);

	//[31:30] skip_dram_init
	//00 - SDRAM Initialization routine is run after power-up
	//01 - SDRAM Initialization routine is skipped after power-up.The controller starts up in normal Mode
	//25:16 post_cke_x1024
	//Indicates the number of cycles to wait after driving CKE high to start the SDRAM initialization sequence.
	//11:0 pre_cke_x1024
	//Indicates the number of cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence.
	//ApbWriteFun_qussi(ddrs_init0_addr, 0x400f000f);
	ApbWriteFun_qussi(ddrs_init0_addr, 0x40ff00ff);

	rdata =
		(CAS_Latency-CWL) << 2		// rd_odt_delay
		| 1 << 8					// rd_odt_hold		//6
		| 0 << 16					// wr_odt_delay		//0
		| 1 << 24					// wr_odt_hold		//6
		;
	ApbWriteFun_qussi(ddrs_odtcfg_addr, rdata); // new add 20240925

#if 1	//RBC
	tmp = (8 << 16) | (8 << 8) | (8 << 0);
	ApbWriteFun(ddrs_addrmap1_addr, tmp);

	tmp = (0x0 << 24) | (0x0 << 16) | (0x0 << 8) | (0x0 << 0);
	ApbWriteFun(ddrs_addrmap2_addr, tmp);

	tmp = (0x0 << 24) | (0x0 << 16) | (0x0 << 8) | (0x0 << 0);
	ApbWriteFun(ddrs_addrmap3_addr, tmp);

	tmp  = (0x1f << 24) | (0x1f << 16) | (0x1f << 8) | (0x1f << 0);
	ApbWriteFun(ddrs_addrmap4_addr, tmp);

	tmp = (0x7 << 24) | (0x7 << 16) | (0x7 << 8) | (0x7 << 0);
	ApbWriteFun(ddrs_addrmap5_addr, tmp);

//	tmp = (0x0<<24) | (0x0<<16) | (0x0 << 8) | (0x7 << 0);//128M
	tmp = (0x0<<24) | (0x7<<16) | (0x7 << 8) | (0x7 << 0);//512M
	ApbWriteFun(ddrs_addrmap6_addr, tmp);
#endif

#if 0	//BRC
	tmp = (21 << 16) | (21 << 8) | (21 << 0);
	ApbWriteFun(ddrs_addrmap1_addr, tmp);

	tmp = (0x0 << 24) | (0x0 << 16) | (0x0 << 8) | (0x0 << 0);
	ApbWriteFun(ddrs_addrmap2_addr, tmp);

	tmp = (0x0 << 24) | (0x0 << 16) | (0x0 << 8) | (0x0 << 0);
	ApbWriteFun(ddrs_addrmap3_addr, tmp);

	tmp = (0x1f << 24) | (0x1f << 16) | (0x1f << 8) | (0x1f << 0);
	ApbWriteFun(ddrs_addrmap4_addr, tmp);

	tmp = (0x4 << 24) | (0x4 << 16) | (0x4 << 8) | (0X4 << 0);
	ApbWriteFun(ddrs_addrmap5_addr, tmp);

	tmp = (0x0 << 24) | (0x0 << 16) | (0x0 << 8) | (0x4 << 0);
	ApbWriteFun(ddrs_addrmap6_addr, tmp);
#endif

	ApbWriteFun_qussi(ddrs_pctrl_0_addr, 0x1);
	ApbWriteFun_qussi(ddrs_pctrl_1_addr, 0x1);
	ApbWriteFun_qussi(ddrs_pctrl_2_addr, 0x1);
	ApbWriteFun_qussi(ddrs_pctrl_3_addr, 0x1);

	ApbWriteFun(ddrs_pcfg_0_addr, 0x05001);
	ApbWriteFun(ddrs_pcfg_1_addr, 0x013ff);
	ApbWriteFun(ddrs_pcfg_2_addr, 0x013ff);
	ApbWriteFun(ddrs_pcfg_3_addr, 0x013ff);
	ApbWriteFun(ddrs_pcfg_w0_addr, 0x05001);
	ApbWriteFun(ddrs_pcfg_w1_addr, 0x013ff);
	ApbWriteFun(ddrs_pcfg_w2_addr, 0x013ff);
	ApbWriteFun(ddrs_pcfg_w3_addr, 0x013ff);
	ApbWriteFun_qussi(ddrs_pcfgrqos0_0_addr, 0x00020e00);
	ApbWriteFun_qussi(ddrs_pcfgrqos0_1_addr, 0x00000e00);
	ApbWriteFun_qussi(ddrs_pcfgrqos0_2_addr, 0x00000e00);
	ApbWriteFun_qussi(ddrs_pcfgrqos0_3_addr, 0x00000e00);
	ApbWriteFun_qussi(ddrs_pcfgrqos1_0_addr, 0x00010001);
	ApbWriteFun_qussi(ddrs_pcfgrqos1_1_addr, 0xffffffff);
	ApbWriteFun_qussi(ddrs_pcfgrqos1_2_addr, 0xffffffff);
	ApbWriteFun_qussi(ddrs_pcfgrqos1_3_addr, 0xffffffff);
	ApbWriteFun_qussi(ddrs_pcfgwqos0_0_addr, 0x00000e00);
	ApbWriteFun_qussi(ddrs_pcfgwqos0_1_addr, 0x00000e00);
	ApbWriteFun_qussi(ddrs_pcfgwqos0_2_addr, 0x00000e00);
	ApbWriteFun_qussi(ddrs_pcfgwqos0_3_addr, 0x00000e00);
	ApbWriteFun_qussi(ddrs_pcfgwqos1_0_addr, 0xffffffff);
	ApbWriteFun_qussi(ddrs_pcfgwqos1_1_addr, 0xffffffff);
	ApbWriteFun_qussi(ddrs_pcfgwqos1_2_addr, 0xffffffff);
	ApbWriteFun_qussi(ddrs_pcfgwqos1_3_addr, 0xffffffff);

	rval = readl(ddrs_sched_addr);
	rval &= ~((0x7f << 8) | (1 << 2));
	rval |= (0x10 << 8) | (1 << 2);
	ApbWriteFun_qussi(ddrs_sched_addr, rval);

	rval = readl(ddrs_sched1_addr);
	rval &= ~0xff;
	rval |= 0x40;
	ApbWriteFun(ddrs_sched1_addr, rval);

	ApbWriteFun_qussi(ddrs_per1_addr, 0xff000001);
	ApbWriteFun_qussi(ddrs_per2_addr, 0x0800007f);
	ApbWriteFun_qussi(ddrs_per3_addr, 0x0800007f);

	ApbWriteFun_qussi(ddrs_dfimisc_addr, 0x0);

	//PHY Timing Register
	tmp = (534 << 21) | (62134 << 6) | (63 << 0);
	ApbWriteFun(ddrsphy_ptr0_addr, tmp);			//PTR0, phy reset = 32

	//ApbWriteFun(0x5150002C, 0x04B05F40);			//PTR4, DRAM Initial,RESET=1/RESET=0
	ApbWriteFun(ddrsphy_ptr4_addr, 0x0ff3ffff);		//PTR4, DRAM Initial,RESET=1/RESET=0
	//ApbWriteFun(ddrsphy_pgcr2_addr, 0x0ff3ffff);	//PTR4, DRAM Initial,RESET=1/RESET=0

	rdata = *((volatile unsigned int *)(ddrsphy_pgcr2_addr));
	rdata &= ~((0xf << 24) | 0x3FFFF);
	rdata |= (0xf << 24) | 0x2000;
	ApbWriteFun(ddrsphy_pgcr2_addr, rdata);
	udelay(100);

	// ApbWriteFun(0x51500068, 0x9F0035c7);			//DTCR,Data Training Configuration Register
	//ApbWriteFun(ddrsphy_dtcr_addr, 0x914075c7);		//DTCR,Data Training Configuration Register
	ApbWriteFun(ddrsphy_dtcr_addr, 0x914035c7);		//DTCR,Data Training Configuration Register
	//ApbWriteFun(0x51500068, 0x914075c7);			//DTCR,Data Training Configuration Register
	//phy parameters
	// ApbWriteFun(0x51500040, 0xF000645F);			//DSGCR,DDR System General Configuration Register,rr_mode=0, dqs gate extension
	ApbWriteFun(ddrsphy_dsgcr_addr, 0xF000641F);	//DSGCR,DDR System General Configuration Register,rr_mode=0
	//ApbWriteFun(0x51500040, 0xF004641F);			//DSGCR,DDR System General Configuration Register,rr_mode=1
	ApbWriteFun(ddrsphy_dcr_addr, 0x0000040B);		//DCR, 8-bank,DDR-MODE=DDR3

	rdata = *((volatile unsigned int *)(ddrsphy_dxccr_addr));
	rdata &= ~((1 << 0) | (3 << 13));
	rdata |= (1 << 0) | (3 << 13);
	ApbWriteFun(ddrsphy_dxccr_addr, rdata);
	//DRAM Timing Parameters Register
	//These timing parameters are in DRAM clock cycles
	//DTPR0
	//[3:0] tRTP 8
	//[7:4] tWTR 8
	//[11:8] tRP 11
	//[15:12] tRCD 11
	//[21:16] tRAS 32
	//[25:22] tRRD 8
	//[31:26] tRC 43
	//ApbWriteFun(0x51500048, 0xc226ee88);//DTPR0
	//DTPR0 DRAM Timing Parameter Register 0
	rdata = 0
		| (TRTP << 0)		//	[3:0] tRTP Internal read to precharge command delay. Valid values are 2 to 15.
		| (tWTR << 4)		//	[7:4] tWTR Internal write to read command delay. Valid values are 1 to 15.
		| (tRP << 8)		//	[11:8] tRP Precharge command period: The minimum time between a precharge command and any other command.
		| (tRCD << 12)		//	[15:12] tRCD Activate to read or write delay.
		| (TRAS << 16)		//	[21:16] tRAS Activate to precharge command delay.
		| (tRRD << 22)		//	[25:22] tRRD Activate to activate command delay (different banks).
		| (TRC << 26)		//	[31:26] tRC Activate to activate command delay (same bank).
		;
	ApbWriteFun(ddrsphy_dtpr0_addr, rdata);		//	0x012 ¨C 0x014 DTPR0-2

	//printf("ddrsphy_dtpr0_addr:TRTP 0x%x,tWTR 0x%x,tRP 0x%x,tRCD 0x%x,TRAS 0x%x,tRRD 0x%x,TRC 0x%x\n", TRTP,tWTR,tRP,tRCD,TRAS,tRRD,TRC);
	//udelay(100);

	//ApbWriteFun(0x51500048, 0xc21dee88);//DTPR0
	//DTPR1
	//[1:0]		tMRD	0
	//[4:2]		tMOD	0
	//[10:5]	tFAW	24
	//[19:11]	tRFC	58
	//[25:20]	tWLMRD
	//[29:26]	tWLO
	//[31:30]	tAOND
	//ApbWriteFun(0x5150004C, 0x1a8373cc);//DTPR1

	unsigned int tMOD;

	if (TMOD == 12)
		tMOD = 0;
	else if (TMOD == 13)
		tMOD = 1;
	else if (TMOD == 14)
		tMOD = 2;
	else if (TMOD == 15)
		tMOD = 3;
	else if (TMOD == 16)
		tMOD = 4;
	else if (TMOD == 17)
		tMOD = 5;
	else
		tMOD = 0;

	rdata = 0
		| ((tMRD - 4) << 0)					//	[1:0] tMRD Load mode cycle time: The minimum time between a load mode register command
												//	and any other command. For DDR3 this is the minimum time between two load mode register commands.
												//	For DDR3, the value used for tMRD is 4 plus the value programmed in these bits,
												//	i.e. tMRD value for DDR3 ranges from 4 to 7.
		| (tMOD << 2)							//	[4:2] tMOD Load mode update delay (DDR3 only). The minimum time between a load mode
												//	register command and a non-load mode register command. Valid values are:
												//	000 = 12
												//	001 = 13
												//	010 = 14
												//	011 = 15
												//	100 = 16
												//	101 = 17
												//	110 ¨C 111 = Reserved
		| (DDR_CALC(40) << 5)					//	[10:5] tFAW 4-bank activate period. No more than 4-bank activate commands may be issued in a
												//	given tFAW period. Only applies to 8-bank devices. Valid values are 2 to 63.
												//	tFAW 40 ns
		| (DDR_CALC(110) << 11)					//	[19:11] tRFC Refresh-to-Refresh: Indicates the minimum time, in clock cycles, between two
												//	refresh commands or between a refresh and an active command
		| (40 << 20)							//	[25:20] tWLMRD Minimum delay from when write leveling mode is programmed to the first
												//	DQS/DQS# rising edge (40 nCK)
		| (0 << 26)							//	[29:26] tWLO Write leveling output delay:
												//	tWLO 0 7.5 ns
		| (0x00 << 30)							//	[31:30] tAOND/tAOFD ODT turn-on/turn-off delays (DDR2 only).
		;
	ApbWriteFun(ddrsphy_dtpr1_addr,  rdata);	//	0x012 ¨C 0x014 DTPR0-2

	//printf("ddrsphy_dtpr1_addr:tMRD 0x%x,tMOD 0x%x,tFAW 0x%x,tRFC 0x%x\n", (tMRD - 4),tMOD,DDR_CALC(40),DDR_CALC(110));

	//ApbWriteFun(0x5150004C, 0x1a83742c);//DTPR1

	//DTPR2
	//[9:0]	tXS Self refresh exit delay. The minimum time between a self refresh exit command and
	//[14:10] tXP Power down exit delay. The minimum time between a power down exit command
	//[18:15] tCKE CKE minimum pulse width. Also specifies the minimum time that the SDRAM must
	//[28:19] tDLLK DLL locking time. Valid values are 2 to 1023. 512
	//[29]	tRTODT Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled
	//[30]	tRTW Read to Write command delay. Valid values are:
	//[31]	tCCD Read to read and write to write command delay. Valid values are:

	// ApbWriteFun(0x51500050, 0x1003e078);//DTPR2
	// DTPR2
	rdata = 0
		| (max(5u, DDR_CALC(110 + 10)) << 0)					//[9:0] tXS Self refresh exit delay.
															//tXSmin: max(5 tCK, tRFC(min) + 10ns)
															//tRFC 110 ns
		| (TXP << 10)										//[14:10] tXP Power down exit delay.
															//tXPmin: max(3tCK, 6ns)
		| (max(3u, DDR_CALC(5)) << 15)						//[18:15] tCKE CKE minimum pulse width.
															//tCKE min: max(3tCK, 5ns)
		| (512 << 19)										//[28:19] tDLLK DLL locking time. Valid values are 2 to 1023. (tDLLK 512 nCK)
		| (0x01 << 29)										//[29] tRTODT Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled
															//immediately after the read post-amble or one clock delay has to be added. Valid
															//values are:
															//0 = ODT may be turned on immediately after read post-amble
															//1 = ODT may not be turned on until one clock after the read post-amble
															//If tRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is
															//enabled.
		| (0x01 << 30)										//[30] tRTW Read to Write command delay. Valid values are:
															//0 = standard bus turn around delay
															//1 = add 1 clock to standard bus turn around delay
															//This parameter allows the user to increase the delay between issuing Write
															//commands to the SDRAM when preceded by Read commands. This provides an
															//option to increase bus turn-around margin for high frequency systems.
		| (0x01UL << 31)										//[31] tCCD Read to read and write to write command delay. Valid values are:
															//0 = BL/2 for DDR2 and 4 for DDR3
															//1 = BL/2 + 1 for DDR2 and 5 for DDR3
															//tCCD 4 - 4 - nCK
		;
	ApbWriteFun(ddrsphy_dtpr2_addr,  rdata);				//  0x012 ¨C 0x014 DTPR0-2

//	printf("ddrsphy_dtpr2_addr:0x%x\n", rdata);

	// step 4
	ApbWriteFun(ddrsphy_pir_addr, 0x33); //[0-INIT]£¬[1-ZCAL][4-PLLINIT][5-DCAL]

	timeout = 100;
	while (timeout--) {
		udelay(20);
		rdata = *((volatile unsigned int *)(ddrsphy_pgsr0_addr));
		if ((rdata & 0x0F) == 0xf)
			break;
	}
	if (timeout < 0 && retries--) {
		printf("DDR_Init step4 timeout, retry...\n");
		goto restart;
	}
	if (retries < 0) {
		printf("DDR_Init step4 fail!\n");
		return;
	}

//	rdata = *((volatile unsigned int *)(ddrsphy_zq0sr0_addr));
//	printf("ddrsphy_zq0sr0_addr:0x%x\n",rdata );

	rdata	=
		(tras_min << 0)			//5:0	t_ras_min
		|	(tras_max << 8)		//14:8  t_ras_max,Specifies the maximum time between activate and precharge to same bank
		|	(tfaw  << 16)		//21:16 t_faw
		|	(wr2pre << 24)		//30:24 wr2pre
		;						//Specifications: WL + BL/2 + tWR

	ApbWriteFun_qussi(ddrs_dramtmg0_addr, rdata);

//	printf("ddrs_dramtmg0_addr:tras_min 0x%x,tras_max 0x%x,tfaw 0x%x,wr2pre 0x%x\n", tras_min,tras_max,tfaw,wr2pre);

	//ApbWriteFun(ddrs_dramtmg0_addr, 0x150f4411);
	//rdata = *((volatile unsigned int *)(ddrs_dramtmg0_addr));

	//20:16 t_xp,Specifies the minimum time after power-down exit to any operation.
	//13:8	rd2pre=tRTP,
	//		DDR3 - tAL + max (RoundUp(tRTP/tCK), 4)
	//6:0	t_rc,Specifies the minimum time between activates to same bank.
	//		tRC/2
	//ApbWriteFun(ddrs_dramtmg1_addr, 0x00020614);

	rdata =
		(trc << 0)				//6:0	t_rc,Specifies the minimum time between activates to same bank.
								//		tRC/2
		| (trtp << 8)			//13:8	rd2pre=tRTP,
								//		DDR3 - tAL + max (RoundUp(tRTP/tCK), 4)
		| (txp << 16)		//20:16	t_xp,Specifies the minimum time after power-down exit to any operation.
		;

	ApbWriteFun_qussi(ddrs_dramtmg1_addr, rdata);

//	printf("ddrs_dramtmg1_addr:trc 0x%x,trtp 0x%x,txp 0x%x\n", trc,trtp,txp);

	//ApbWriteFun(ddrs_dramtmg1_addr, 0x00030818);
	// rdata = *((volatile unsigned int *)(ddrs_dramtmg1_addr));

	//WL/RL
	//29:24 write_latency=WL
	//		This register field is not required for DDR2 and DDR3, as the
	//		DFI read and write latencies defined in DFITMG0 and
	//		DFITMG1 are sufficient for those protocols
	//21:16 read_latency=RL
	//		This register field is not required for DDR2 and DDR3, as the
	//		DFI read and write latencies defined in DFITMG0 and
	//		DFITMG1 are sufficient for those protocols
	//13:8	rd2wr,Minimum time from read command to write command
	//		DDR2/3/mDDR: RL + BL/2 + 2 - WL
	//5:0	wr2rd.
	//		CWL + BL/2 + tWTR
	//	For DDR3:
	//	RL = CL + AL
	//	WL = CWL + AL
	//ApbWriteFun(ddrs_dramtmg2_addr, 0x0305080f);

	//WL/RL
	rdata	=
		(((CWL + 4 + twtr + 1) / 2) << 0)		//5:0   wr2rd.
											//      CWL + BL/2 + tWTR
		| (((RL + 6 - WL + 1) / 2) << 8)		//13:8  rd2wr,Minimum time from read command to write command
											//      DDR2/3/mDDR: RL + BL/2 + 2 - WL
		| (((RL + 1) / 2) << 16)					//21:16 read_latency=RL
											//This register field is not required for DDR2 and DDR3, as the
											//DFI read and write latencies defined in DFITMG0 and
											//DFITMG1 are sufficient for those protocols
		| (((WL + 1) / 2) << 24)					//29:24 write_latency=WL
											//This register field is not required for DDR2 and DDR3, as the
											//DFI read and write latencies defined in DFITMG0 and
		;
	ApbWriteFun_qussi(ddrs_dramtmg2_addr, rdata);

	//ApbWriteFun(ddrs_dramtmg2_addr, 0x050e0f1A);
	//rdata = *((volatile unsigned int *)(ddrs_dramtmg2_addr));

	rdata =
		(((TMOD + 1) / 2) << 0)
		| (((tMRD + 1) / 2) << 12)
		;
	ApbWriteFun_qussi(ddrs_dramtmg3_addr, rdata);
	//ApbWriteFun(ddrs_dramtmg3_addr, 0x0000400f);
	//rdata = *((volatile unsigned int *)(ddrs_dramtmg3_addr));

	//28:24 t_rcd, Indicates the minimum time from activate to read or write command to same bank.
	//19:16 t_ccd, is the minimum time between two reads or two writes.
	//11:8  t_rrd, Minimum time between activates from bank "a" to bank "b"
	//4:0   t_rp,  Indicates the minimum time from single-bank precharge to activate of same bank.

	rdata =
		(((tRP + 1) / 2) << 0)       //4:0   t_rp,  Indicates the minimum time from single-bank precharge to activate of same bank.

		| (((tRRD + 1) / 2) << 8)			//11:8  t_rrd, Minimum time between activates from bank "a" to bank "b"

		| (2 << 22)					//19:16 t_ccd, is the minimum time between two reads or two writes.

		| (((tRCD + 1) / 2) << 24)		//28:24 t_rcd, Indicates the minimum time from activate to read or write command to same bank.
		;
	ApbWriteFun_qussi(ddrs_dramtmg4_addr, rdata);

	//printf("ddrs_dramtmg4_addr:0x%x\n", rdata);

	//ApbWriteFun(ddrs_dramtmg4_addr, 0x06040407);

	rdata =
		(tCKE << 0)						// tCKE
		| ((tCKE + 1) << 8)				// tCKESR = tCKE + 1
		| (((tCKSRX + 1) / 2) << 16)		// tCKSRE
		| (((tCKSRX + 1) / 2) << 24)		// tCKSRX
		;

	ApbWriteFun_qussi(ddrs_dramtmg5_addr, rdata);
	//ApbWriteFun(ddrs_dramtmg5_addr, 0x0a0a0403);

	rdata =
		((tXS + 1) << 0)				// tXS  x 32
		| (8 << 8)					// tXSDLL x 32 = 512 / (2*32)
	;

	ApbWriteFun_qussi(ddrs_dramtmg8_addr, rdata);
	//ApbWriteFun(ddrs_dramtmg8_addr, 0x00001406);

	//28:24 dfi_t_ctrl_delay
	//22:16 dfi_t_rddata_en
	//13:8  dfi_tphy_wrdata
	//5:0   dfi_tphy_wrlat
	//ApbWriteFun(ddrs_dfitmg0_addr, 0x02020102);

	// DFITRDDATAEN
	// trddata_en
	rdata	=
	(((WL - 3) / 2) << 0)		// dfi_tphy_wrlat
	| (1 << 8)					// dfi_tphy_wrdata
	| (((RL - 3) / 2) << 16)	// dfi_t_rddata_en
	| (2 << 24)					// dfi_t_ctrl_delay
	;
	ApbWriteFun_qussi(ddrs_dfitmg0_addr, rdata);
//	delay(3000);
	//DFITMG1
	//31:28 dfi_t_cmd_lat
	//20:16 dfi_t_wrdata_delay
	//12:8  dfi_t_dram_clk_disable
	ApbWriteFun_qussi(ddrs_dfitmg1_addr, 0x01010202);

	timeout = 100;
	while (timeout--) {
		udelay(20);
		rdata = *((volatile unsigned int *)(ddrs_stat_addr));
		if ((rdata & 0x03) == 0x01)
			break;
	}
	if (timeout < 0 && retries--) {
		printf("DDR_Init step10 timeout, retry...\n");
		goto restart;
	}
	if (retries < 0) {
		printf("DDR_Init step10 fail!\n");
		return;
	}

	ApbWriteFun_qussi(ddrs_rfshctl3_addr, 0x1);
	ApbWriteFun_qussi(ddrs_rfshtmg_addr, 0x88002c);
	ApbWriteFun_qussi(ddrs_pwrctl_addr, 0x00);

	mrdata = 0
			| MR2_CWL
			| MCTL_MR2_Rtt_WR_RZQ_4;
	ApbWriteFun(ddrsphy_mr2_addr,  mrdata);
	ApbWriteFun(ddrsphy_mr3_addr, 0x00000000);

	mrdata	= 0
		| MCTL_MR1_DLL_Enable
		| MCTL_MR1_DIC_RZQ_7		// Output Driver Impedance Control
		| MCTL_MR1_Rtt_Nom_RZQ_6	// If RTT_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
#if AL_0
		| MCTL_MR1_AL_0_disabled
#elif AL_1
		| MCTL_MR1_AL_CL_1
#elif AL_2
		| MCTL_MR1_AL_CL_2
#endif

		//| MCTL_MR1_Write_leveling_Enabled
		| MCTL_MR1_Write_leveling_Disabled
		| MCTL_MR1_Qoff_Output_buffer_enabled
		;
	ApbWriteFun(ddrsphy_mr1_addr,  mrdata);

	unsigned int WR_cycle;

	if (WR == 16)
		WR_cycle = 0;
	else if (WR == 5)
		WR_cycle = 1;
	else if (WR == 6)
		WR_cycle = 2;
	else if (WR == 7)
		WR_cycle = 3;
	else if (WR == 8)
		WR_cycle = 4;
	else if (WR == 10)
		WR_cycle = 5;
	else if (WR == 12)
		WR_cycle = 6;
	else if (WR == 14)
		WR_cycle = 7;
	else
		return;

	mrdata = 0
		| MCTL_MR0_BL_8_Fixed
		| MR0_CL
		| MCTL_MR0_TM_Normal
		| MCTL_MR0_DLL_Reset_Yes
		| MCTL_MR0_WR(WR_cycle)
		| MCTL_MR0_PPD_Fast_exit
		;
	ApbWriteFun(ddrsphy_mr0_addr, mrdata);		// 0x015 MR0

	udelay(1000);
	ApbWriteFun(ddrsphy_pir_addr, 0x00050ff3);

	udelay(3000);
	// step 16

	timeout = 100;
	while (timeout--) {
		udelay(20);
		rdata = *((volatile unsigned int *)(ddrsphy_pgsr0_addr));
		//PrintVariableValueHex("ddrsphy_pgsr0_addr : ", rdata);
		if (rdata == 0x900000ff)
			break;
	}
	if (timeout < 0 && retries--) {
		printf("DDR_Init step16 timeout, retry...\n");
		goto restart;
	}
	if (retries < 0) {
		printf("DDR_Init step16 fail!\n");
		return;
	}

	ApbWriteFun_qussi(ddrs_rfshctl3_addr, 0x0);
	ApbWriteFun(ddrs_swctlstatic_addr, 0x0);
}

void ddr3_sdramc_init(void)
{
	ddr_init();
}