ark1668ed-bsp/u-boot/arch/arm/mach-arkmicro/spl_ark1668ed.c

// SPDX-License-Identifier: GPL-2.0+

#include <common.h>
#include <linux/delay.h>
#include <init.h>
#include <spl.h>
#include <asm/arch/timer.h>
#include <asm/arch/ark1668ed-sysreg.h>
#include <asm/arch/ark-common.h>
#include <asm-generic/gpio.h>
#if CONFIG_IS_ENABLED(BANNER_PRINT)
#include <timestamp.h>
#endif
#include <version.h>


#define BOOT_SAMPLE_CPUPLL_LOCK		(1 << 30)
#define BOOT_SAMPLE_SYSPLL_LOCK		(1 << 29)
#define BOOT_SAMPLE_VPUPLL_LOCK		(1 << 28)
#define BOOT_SAMPLE_DDRPLL_LOCK		(1 << 27)
#define BOOT_SAMPLE_MFCPLL_LOCK		(1 << 26)
#define BOOT_SAMPLE_AHBPLL_LOCK		(1 << 25)
#define BOOT_SAMPLE_GPUPLL_LOCK		(1 << 24)

#define BOOT_SAMPLE_DSPPLL_LOCK		(1 << 23)
#define BOOT_SAMPLE_TVPLL_LOCK		(1 << 22)

#define DDR_CTL1_CPUPLL_EN			(1 << 1)
#define DDR_CTL1_SYSPLL_EN			(1 << 3)
#define DDR_CTL1_DDRPLL_EN			(1 << 5)
#define DDR_CTL1_VPUPLL_EN			(1 << 7)
#define DDR_CTL1_MFCPLL_EN			(1 << 9)
#define DDR_CTL1_AHBPLL_EN			(1 << 11)

void clk_init(void)
{
	uint32_t timeout = 1000;

	rSYS_BUS_CLK_CFG &= ~0x3F;
	rSYS_DDR_CTL1_CFG &= ~0x1ff;
	rSYS_CPUPLL_CFG |= 0xf << 26;
	rSYS_SYSPLL_CFG |= 0xf << 26;
	rSYS_VPUPLL_CFG |= 0xf << 26;
	rSYS_DDRPLL_CFG |= 0xf << 26;
	rSYS_MFCPLL_CFG |= 0xf << 26;
	rSYS_TVPLL_CFG |= 0xf << 26;
	rSYS_AHBPLL_CFG |= 0xf << 26;
	rSYS_GPUPLL_CFG |= 0xf << 26;
	udelay(100);

	/* cpu pll (注：硬件不支持扩频，DSMPD位无效)*/
	rSYS_CPUPLL_CFG = (1 << 27) | (1 << 23) | (1 << 20) | (100 << 8) | 3;   //800M

	/* sys pll (注：硬件支持扩频。 DSMPD位有效，需要延时配置)*/
	rSYS_SYSPLL_SPRD_CTL |= (1 << 30);// 扩频器bypass
	rSYS_SYSPLL_CFG = (1 << 23) | (2 << 20) | (90 << 8) | (3 << 0);
	udelay(100);
	rSYS_SYSPLL_CFG |= 1 << 27;

	/* vpu pll (注：硬件支持扩频。 DSMPD位有效，需要延时配置)*/
	rSYS_VPUPLL_SPRD_CTL |= (1 << 30);// 扩频器bypass
	rSYS_VPUPLL_CFG = (1 << 23) | (2 << 20) | (100 << 8) | (4 << 0);
	udelay(100);
	rSYS_VPUPLL_CFG |= 1 << 27;

	// ddr pll (注：硬件不支持扩频，DSMPD位无效)*/
	rSYS_DDRPLL_CFG = (1 << 27) | (1 << 23) | (3 << 20) | (200 << 8) | 4;  // 300M

	// mfc pll (注：硬件不支持扩频，DSMPD位无效)
	rSYS_MFCPLL_CFG = (1 << 27) | (1 << 23) | (2 << 20) | (500<< 8) | 6;  //1000M

	// tv pll (注：硬件不支持扩频，DSMPD位无效)
	//rSYS_TVPLL_CFG = (1 << 27) | (1 << 23) | (6 << 20) | (297 << 8) | 4;	//297M
	rSYS_TVPLL_CFG = (1 << 27) | (1 << 23) | (2 << 20) | (144 << 8) | 4;	//432M

	// ahb pll (注：硬件支持扩频。 DSMPD位有效，需要延时配置)
	rSYS_AHBPLL_SPRD_CTL |= (1 << 30);// 扩频器bypass
	rSYS_AHBPLL_CFG = (1 << 23) | (4 << 20) | (135 << 8) | 3;
	udelay(100);
	rSYS_AHBPLL_CFG |= 1 << 27;

	// gpu pll (注：硬件不支持扩频，DSMPD位无效)
	rSYS_GPUPLL_CFG = (1 << 27) | (1 << 23) | (2 << 20) | (200 << 8) | 3;

	// wait cpupll lock
	while (!(rSYS_BOOT_SAMPLE & BOOT_SAMPLE_CPUPLL_LOCK) && timeout--)
		udelay(1);

	//wait syspll lock
	timeout = 1000;
	while (!(rSYS_BOOT_SAMPLE & BOOT_SAMPLE_SYSPLL_LOCK) && timeout--)
		udelay(1);

	//wait vpupll lock
	timeout = 1000;
	while (!(rSYS_BOOT_SAMPLE & BOOT_SAMPLE_VPUPLL_LOCK) && timeout--)
		udelay(1);

	// wait ddrpll lock
	timeout = 1000;
	while (!(rSYS_BOOT_SAMPLE & BOOT_SAMPLE_DDRPLL_LOCK) && timeout--)
		udelay(1);

	//wait mfcpll lock
	timeout = 1000;
	while (!(rSYS_BOOT_SAMPLE & BOOT_SAMPLE_MFCPLL_LOCK) && timeout--)
		udelay(1);

	// wait ahbpll lock
	timeout = 1000;
	while (!(rSYS_BOOT_SAMPLE & BOOT_SAMPLE_AHBPLL_LOCK) && timeout--)
		udelay(1);

	//wait gpupll lock
	timeout = 1000;
	while (!(rSYS_BOOT_SAMPLE & BOOT_SAMPLE_GPUPLL_LOCK) && timeout--)
		udelay(1);

	//wait tvpll lock
	timeout = 1000;
	while (!(rSYS_BOOT_SAMPLE & BOOT_SAMPLE_TVPLL_LOCK) && timeout--)
		udelay(1);

	udelay(1000);
	//clk gate enable
	rSYS_DDR_CTL1_CFG |=
		(1 << 8) |		//TVPLL enable
		(1 << 7) |		//GPUPLL enable
		(1 << 6) |		//AHBPLL enable
		(1 << 5) |		//MFCPLL enable
		(1 << 4) |		//VPUPLL enable
		(1 << 3) |		//DDRPLL enable
		(1 << 2) |		//SYSPLL enable
		(1 << 1) |		//DSPPLL enable
		(1 << 0);		//CPUPLL enable
	udelay(1);

	rSYS_BUS_CLK_CFG |=
		(1 << 4) |		//pclk to hclk/2
		(1 << 3) |		//hclk to AHBPLL
		(1 << 2) |		//xclk to SYSPLL
		(1 << 1) |		//dclk to DDRPLL
		(1 << 0);		//cclk to CPUPLL

	printf("rSYS_BOOT_SAMPLE = 0x%x\n", rSYS_BOOT_SAMPLE);

}
 static void switch_to_main_crystal_osc(void)
{

	clk_init();
	return;
}

void board_init_f(ulong dummy)
{
	timer_init();
	board_early_init_f();
	puts("\nU-Boot " SPL_TPL_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - "U_BOOT_TIME " " U_BOOT_TZ ")\n");
	switch_to_main_crystal_osc();
	ddr3_sdramc_init();
}
#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
void puts(const char *s)
{
	serial_puts(s);
}
void putc(const char c)
{
	serial_putc(c);
}
#endif
#ifndef CONFIG_SPL_LIBGENERIC_SUPPORT
void udelay(unsigned long usec)
{
	timer_delay_us(usec);
}
void hang(void)
{
	for (;;)
		;
}
uint32_t __div64_32(uint64_t *n, uint32_t base)
{
    uint64_t rem = *n;
    uint64_t b = base;
    uint64_t res, d = 1;
    uint32_t high = rem >> 32;
    /* Reduce the thing a bit first */
    res = 0;
    if (high >= base) {
		high /= base;
		res = (uint64_t) high << 32;
		rem -= (uint64_t) (high*base) << 32;
    }
    while ((int64_t)b > 0 && b < rem) {
		b = b+b;
		d = d+d;
    }
    do {
		if (rem >= b) {
		    rem -= b;
		    res += d;
		}
		b >>= 1;
		d >>= 1;
    } while (d);
    *n = res;
    return rem;
}
void * memmove(void * dest, const void *src, size_t count)
{
    char *tmp, *s;

    if (dest <= src) {
		memcpy(dest, src, count);
    } else {
		tmp = (char *) dest + count;
		s = (char *) src + count;
		while (count--)
		    *--tmp = *--s;
	}
    return dest;
}
#endif