t1024rdb.dts 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * T1024RDB Device Tree Source
  4. *
  5. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019-2023 NXP
  7. */
  8. /include/ "t102x.dtsi"
  9. / {
  10. model = "fsl,T1024RDB";
  11. compatible = "fsl,T1024RDB";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. aliases {
  16. sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
  17. serial0 = &serial0;
  18. serial1 = &serial1;
  19. serial2 = &serial2;
  20. serial3 = &serial3;
  21. spi0 = &espi0;
  22. };
  23. soc: soc@ffe000000 {
  24. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  25. reg = <0xf 0xfe000000 0 0x00001000>;
  26. fman@400000 {
  27. fm1mac1: ethernet@e0000 {
  28. phy-handle = <&xg_aqr105_phy3>;
  29. phy-connection-type = "xgmii";
  30. };
  31. fm1mac2: ethernet@e2000 {
  32. };
  33. fm1mac3: ethernet@e4000 {
  34. phy-handle = <&rgmii_phy2>;
  35. phy-connection-type = "rgmii";
  36. };
  37. fm1mac4: ethernet@e6000 {
  38. phy-handle = <&rgmii_phy1>;
  39. phy-connection-type = "rgmii";
  40. };
  41. mdio0: mdio@fc000 {
  42. rgmii_phy1: ethernet-phy@2 {
  43. reg = <0x2>;
  44. };
  45. rgmii_phy2: ethernet-phy@6 {
  46. reg = <0x6>;
  47. };
  48. };
  49. xmdio0: mdio@fd000 {
  50. xg_aqr105_phy3: ethernet-phy@1 {
  51. compatible = "ethernet-phy-ieee802.3-c45";
  52. reg = <0x1>;
  53. };
  54. sg_2500_aqr105_phy4: ethernet-phy@2 {
  55. compatible = "ethernet-phy-ieee802.3-c45";
  56. reg = <0x2>;
  57. };
  58. };
  59. };
  60. };
  61. };
  62. &espi0 {
  63. status = "okay";
  64. flash@0 {
  65. compatible = "jedec,spi-nor";
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. reg = <0>;
  69. /* input clock */
  70. spi-max-frequency = <10000000>;
  71. };
  72. };
  73. #include "t1024si-post.dtsi"