cache.c 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <asm/cache.h>
  9. #include <watchdog.h>
  10. static ulong maybe_watchdog_reset(ulong flushed)
  11. {
  12. flushed += CONFIG_SYS_CACHELINE_SIZE;
  13. if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) {
  14. schedule();
  15. flushed = 0;
  16. }
  17. return flushed;
  18. }
  19. void flush_cache(ulong start_addr, ulong size)
  20. {
  21. ulong addr, start, end;
  22. ulong flushed = 0;
  23. start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  24. end = start_addr + size - 1;
  25. for (addr = start; (addr <= end) && (addr >= start);
  26. addr += CONFIG_SYS_CACHELINE_SIZE) {
  27. asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
  28. flushed = maybe_watchdog_reset(flushed);
  29. }
  30. /* wait for all dcbst to complete on bus */
  31. asm volatile("sync" : : : "memory");
  32. for (addr = start; (addr <= end) && (addr >= start);
  33. addr += CONFIG_SYS_CACHELINE_SIZE) {
  34. asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
  35. flushed = maybe_watchdog_reset(flushed);
  36. }
  37. asm volatile("sync" : : : "memory");
  38. /* flush prefetch queue */
  39. asm volatile("isync" : : : "memory");
  40. }