test.dts 34 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Devicetree file for running sandbox tests
  4. *
  5. * This includes lots of extra devices used by various tests.
  6. *
  7. * Note that SPL use the main sandbox.dts file
  8. */
  9. /dts-v1/;
  10. #include <dt-bindings/gpio/gpio.h>
  11. #include <dt-bindings/gpio/sandbox-gpio.h>
  12. #include <dt-bindings/input/input.h>
  13. #include <dt-bindings/pinctrl/sandbox-pinmux.h>
  14. #include <dt-bindings/mux/mux.h>
  15. / {
  16. model = "sandbox";
  17. compatible = "sandbox";
  18. #address-cells = <1>;
  19. #size-cells = <1>;
  20. aliases {
  21. console = &uart0;
  22. ethernet0 = "/eth@10002000";
  23. ethernet2 = &swp_0;
  24. ethernet3 = &eth_3;
  25. ethernet4 = &dsa_eth0;
  26. ethernet5 = &eth_5;
  27. ethernet6 = "/eth@10004000";
  28. ethernet7 = &swp_1;
  29. ethernet8 = &phy_eth0;
  30. gpio1 = &gpio_a;
  31. gpio2 = &gpio_b;
  32. gpio3 = &gpio_c;
  33. i2c0 = "/i2c@0";
  34. mmc0 = "/mmc0";
  35. mmc1 = "/mmc1";
  36. mmc2 = "/mmc2";
  37. mmc3 = "/mmc3";
  38. pci0 = &pci0;
  39. pci1 = &pci1;
  40. pci2 = &pci2;
  41. remoteproc0 = &rproc_1;
  42. remoteproc1 = &rproc_2;
  43. rtc0 = &rtc_0;
  44. rtc1 = &rtc_1;
  45. spi0 = "/spi@0";
  46. testfdt6 = "/e-test";
  47. testbus3 = "/some-bus";
  48. testfdt0 = "/some-bus/c-test@0";
  49. testfdt12 = "/some-bus/c-test@1";
  50. testfdt3 = "/b-test";
  51. testfdt5 = "/some-bus/c-test@5";
  52. testfdt8 = "/a-test";
  53. testfdtm1 = &testfdtm1;
  54. fdt-dummy0 = "/translation-test@8000/dev@0,0";
  55. fdt-dummy1 = "/translation-test@8000/dev@1,100";
  56. fdt-dummy2 = "/translation-test@8000/dev@2,200";
  57. fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
  58. usb0 = &usb_0;
  59. usb1 = &usb_1;
  60. usb2 = &usb_2;
  61. axi0 = &axi;
  62. osd0 = "/osd";
  63. };
  64. binman: binman {
  65. };
  66. config {
  67. testing-bool;
  68. testing-int = <123>;
  69. testing-str = "testing";
  70. environment {
  71. from_fdt = "yes";
  72. fdt_env_path = "";
  73. };
  74. };
  75. bootstd {
  76. bootph-verify;
  77. compatible = "u-boot,boot-std";
  78. filename-prefixes = "/", "/boot/";
  79. bootdev-order = "mmc2", "mmc1";
  80. extlinux {
  81. compatible = "u-boot,extlinux";
  82. };
  83. efi {
  84. compatible = "u-boot,distro-efi";
  85. };
  86. theme {
  87. font-size = <30>;
  88. menu-inset = <3>;
  89. menuitem-gap-y = <1>;
  90. };
  91. /*
  92. * This is used for the VBE OS-request tests. A FAT filesystem
  93. * created in a partition with the VBE information appearing
  94. * before the partition starts
  95. */
  96. firmware0 {
  97. bootph-verify;
  98. compatible = "fwupd,vbe-simple";
  99. storage = "mmc1";
  100. skip-offset = <0x200>;
  101. area-start = <0x400>;
  102. area-size = <0x1000>;
  103. state-offset = <0x400>;
  104. state-size = <0x40>;
  105. version-offset = <0x800>;
  106. version-size = <0x100>;
  107. };
  108. /*
  109. * This is used for the VBE VPL tests. The MMC device holds the
  110. * binman image.bin file. The test progresses through each phase
  111. * of U-Boot, loading each in turn from MMC.
  112. *
  113. * Note that the test enables this node (and mmc3) before
  114. * running U-Boot
  115. */
  116. firmware1 {
  117. bootph-verify;
  118. status = "disabled";
  119. compatible = "fwupd,vbe-simple";
  120. storage = "mmc3";
  121. skip-offset = <0x800000>;
  122. area-start = <0>;
  123. area-size = <0xe00000>;
  124. state-offset = <0xdffc00>;
  125. state-size = <0x40>;
  126. version-offset = <0xdffe00>;
  127. version-size = <0x100>;
  128. };
  129. };
  130. cedit: cedit {
  131. };
  132. cedit-theme {
  133. font-size = <30>;
  134. menu-inset = <3>;
  135. menuitem-gap-y = <1>;
  136. };
  137. fuzzing-engine {
  138. compatible = "sandbox,fuzzing-engine";
  139. };
  140. reboot-mode0 {
  141. compatible = "reboot-mode-gpio";
  142. gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
  143. u-boot,env-variable = "bootstatus";
  144. mode-test = <0x01>;
  145. mode-download = <0x03>;
  146. };
  147. reboot_mode1: reboot-mode@14 {
  148. compatible = "reboot-mode-rtc";
  149. rtc = <&rtc_0>;
  150. reg = <0x30 4>;
  151. u-boot,env-variable = "bootstatus";
  152. big-endian;
  153. mode-test = <0x21969147>;
  154. mode-download = <0x51939147>;
  155. };
  156. audio: audio-codec {
  157. compatible = "sandbox,audio-codec";
  158. #sound-dai-cells = <1>;
  159. };
  160. buttons {
  161. compatible = "gpio-keys";
  162. btn1 {
  163. gpios = <&gpio_a 3 0>;
  164. label = "button1";
  165. linux,code = <BTN_1>;
  166. };
  167. btn2 {
  168. gpios = <&gpio_a 4 0>;
  169. label = "button2";
  170. linux,code = <BTN_2>;
  171. };
  172. };
  173. buttons2 {
  174. compatible = "adc-keys";
  175. io-channels = <&adc 3>;
  176. keyup-threshold-microvolt = <3000000>;
  177. button-up {
  178. label = "button3";
  179. linux,code = <KEY_F3>;
  180. press-threshold-microvolt = <1500000>;
  181. };
  182. button-down {
  183. label = "button4";
  184. linux,code = <KEY_F4>;
  185. press-threshold-microvolt = <1000000>;
  186. };
  187. button-enter {
  188. label = "button5";
  189. linux,code = <KEY_F5>;
  190. press-threshold-microvolt = <500000>;
  191. };
  192. };
  193. cros_ec: cros-ec {
  194. reg = <0 0>;
  195. compatible = "google,cros-ec-sandbox";
  196. /*
  197. * This describes the flash memory within the EC. Note
  198. * that the STM32L flash erases to 0, not 0xff.
  199. */
  200. flash {
  201. image-pos = <0x08000000>;
  202. size = <0x20000>;
  203. erase-value = <0>;
  204. /* Information for sandbox */
  205. ro {
  206. image-pos = <0>;
  207. size = <0xf000>;
  208. };
  209. wp-ro {
  210. image-pos = <0xf000>;
  211. size = <0x1000>;
  212. used = <0x884>;
  213. compress = "lz4";
  214. uncomp-size = <0xcf8>;
  215. hash {
  216. algo = "sha256";
  217. value = [00 01 02 03 04 05 06 07
  218. 08 09 0a 0b 0c 0d 0e 0f
  219. 10 11 12 13 14 15 16 17
  220. 18 19 1a 1b 1c 1d 1e 1f];
  221. };
  222. };
  223. rw {
  224. image-pos = <0x10000>;
  225. size = <0x10000>;
  226. };
  227. };
  228. cros_ec_pwm: cros-ec-pwm {
  229. compatible = "google,cros-ec-pwm";
  230. #pwm-cells = <1>;
  231. };
  232. };
  233. dsi_host: dsi_host {
  234. compatible = "sandbox,dsi-host";
  235. };
  236. a-test {
  237. reg = <0 1>;
  238. compatible = "denx,u-boot-fdt-test";
  239. ping-expect = <0>;
  240. ping-add = <0>;
  241. bootph-all;
  242. test-gpios = <&gpio_a 1>, <&gpio_a 4>,
  243. <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
  244. <0>, <&gpio_a 12>;
  245. test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
  246. <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
  247. <&gpio_b 7 GPIO_IN 3 2 1>,
  248. <&gpio_b 8 GPIO_OUT 3 2 1>,
  249. <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
  250. test3-gpios =
  251. <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
  252. <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
  253. <&gpio_c 2 GPIO_OUT>,
  254. <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
  255. <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
  256. <&gpio_c 5 GPIO_IN>,
  257. <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
  258. <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
  259. test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
  260. test5-gpios = <&gpio_a 19>;
  261. bool-value;
  262. int8-value = /bits/ 8 <0x12>;
  263. int16-value = /bits/ 16 <0x1234>;
  264. int-value = <1234>;
  265. uint-value = <(-1234)>;
  266. int64-value = /bits/ 64 <0x1111222233334444>;
  267. int-array = <5678 9123 4567>;
  268. str-value = "test string";
  269. interrupts-extended = <&irq 3 0>;
  270. acpi,name = "GHIJ";
  271. phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
  272. mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
  273. <&muxcontroller0 2>, <&muxcontroller0 3>,
  274. <&muxcontroller1>;
  275. mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
  276. mux-syscon = <&syscon3>;
  277. display-timings {
  278. timing0: 240x320 {
  279. clock-frequency = <6500000>;
  280. hactive = <240>;
  281. vactive = <320>;
  282. hfront-porch = <6>;
  283. hback-porch = <7>;
  284. hsync-len = <1>;
  285. vback-porch = <5>;
  286. vfront-porch = <8>;
  287. vsync-len = <2>;
  288. hsync-active = <1>;
  289. vsync-active = <0>;
  290. de-active = <1>;
  291. pixelclk-active = <1>;
  292. interlaced;
  293. doublescan;
  294. doubleclk;
  295. };
  296. timing1: 480x800 {
  297. clock-frequency = <9000000>;
  298. hactive = <480>;
  299. vactive = <800>;
  300. hfront-porch = <10>;
  301. hback-porch = <59>;
  302. hsync-len = <12>;
  303. vback-porch = <15>;
  304. vfront-porch = <17>;
  305. vsync-len = <16>;
  306. hsync-active = <0>;
  307. vsync-active = <1>;
  308. de-active = <0>;
  309. pixelclk-active = <0>;
  310. };
  311. timing2: 800x480 {
  312. clock-frequency = <33500000>;
  313. hactive = <800>;
  314. vactive = <480>;
  315. hback-porch = <89>;
  316. hfront-porch = <164>;
  317. vback-porch = <23>;
  318. vfront-porch = <10>;
  319. hsync-len = <11>;
  320. vsync-len = <13>;
  321. };
  322. };
  323. panel-timing {
  324. clock-frequency = <6500000>;
  325. hactive = <240>;
  326. vactive = <320>;
  327. hfront-porch = <6>;
  328. hback-porch = <7>;
  329. hsync-len = <1>;
  330. vback-porch = <5>;
  331. vfront-porch = <8>;
  332. vsync-len = <2>;
  333. hsync-active = <1>;
  334. vsync-active = <0>;
  335. de-active = <1>;
  336. pixelclk-active = <1>;
  337. interlaced;
  338. doublescan;
  339. doubleclk;
  340. };
  341. };
  342. junk {
  343. reg = <1 1>;
  344. compatible = "not,compatible";
  345. };
  346. no-compatible {
  347. reg = <2 1>;
  348. };
  349. backlight: backlight {
  350. compatible = "pwm-backlight";
  351. enable-gpios = <&gpio_a 1>;
  352. power-supply = <&ldo_1>;
  353. pwms = <&pwm 0 1000>;
  354. default-brightness-level = <5>;
  355. brightness-levels = <0 16 32 64 128 170 202 234 255>;
  356. };
  357. bind-test {
  358. compatible = "simple-bus";
  359. bind-test-child1 {
  360. compatible = "sandbox,phy";
  361. #phy-cells = <1>;
  362. };
  363. bind-test-child2 {
  364. compatible = "simple-bus";
  365. };
  366. };
  367. b-test {
  368. reg = <3 1>;
  369. compatible = "denx,u-boot-fdt-test";
  370. ping-expect = <3>;
  371. ping-add = <3>;
  372. mux-controls = <&muxcontroller0 0>;
  373. mux-control-names = "mux0";
  374. };
  375. phy_provider0: gen_phy@0 {
  376. compatible = "sandbox,phy";
  377. #phy-cells = <1>;
  378. };
  379. phy_provider1: gen_phy@1 {
  380. compatible = "sandbox,phy";
  381. #phy-cells = <0>;
  382. broken;
  383. };
  384. phy_provider2: gen_phy@2 {
  385. compatible = "sandbox,phy";
  386. #phy-cells = <0>;
  387. };
  388. gen_phy_user: gen_phy_user {
  389. compatible = "simple-bus";
  390. phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
  391. phy-names = "phy1", "phy2", "phy3";
  392. };
  393. gen_phy_user1: gen_phy_user1 {
  394. compatible = "simple-bus";
  395. phys = <&phy_provider0 0>, <&phy_provider2>;
  396. phy-names = "phy1", "phy2";
  397. };
  398. some-bus {
  399. #address-cells = <1>;
  400. #size-cells = <0>;
  401. compatible = "denx,u-boot-test-bus";
  402. reg = <3 1>;
  403. ping-expect = <4>;
  404. ping-add = <4>;
  405. c-test@5 {
  406. compatible = "denx,u-boot-fdt-test";
  407. reg = <5>;
  408. ping-expect = <5>;
  409. ping-add = <5>;
  410. };
  411. c-test@0 {
  412. compatible = "denx,u-boot-fdt-test";
  413. reg = <0>;
  414. ping-expect = <6>;
  415. ping-add = <6>;
  416. };
  417. c-test@1 {
  418. compatible = "denx,u-boot-fdt-test";
  419. reg = <1>;
  420. ping-expect = <7>;
  421. ping-add = <7>;
  422. };
  423. };
  424. d-test {
  425. reg = <3 1>;
  426. ping-expect = <6>;
  427. ping-add = <6>;
  428. compatible = "google,another-fdt-test";
  429. };
  430. e-test {
  431. reg = <3 1>;
  432. ping-expect = <6>;
  433. ping-add = <6>;
  434. compatible = "google,another-fdt-test";
  435. };
  436. f-test {
  437. compatible = "denx,u-boot-fdt-test";
  438. };
  439. g-test {
  440. compatible = "denx,u-boot-fdt-test";
  441. };
  442. h-test {
  443. compatible = "denx,u-boot-fdt-test1";
  444. };
  445. i-test {
  446. compatible = "mediatek,u-boot-fdt-test";
  447. #address-cells = <1>;
  448. #size-cells = <0>;
  449. subnode@0 {
  450. reg = <0>;
  451. };
  452. subnode@1 {
  453. reg = <1>;
  454. };
  455. subnode@2 {
  456. reg = <2>;
  457. };
  458. };
  459. devres-test {
  460. compatible = "denx,u-boot-devres-test";
  461. };
  462. another-test {
  463. reg = <0 2>;
  464. compatible = "denx,u-boot-fdt-test";
  465. test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
  466. test5-gpios = <&gpio_a 19>;
  467. };
  468. mmio-bus@0 {
  469. #address-cells = <1>;
  470. #size-cells = <1>;
  471. compatible = "denx,u-boot-test-bus";
  472. dma-ranges = <0x10000000 0x00000000 0x00040000>;
  473. subnode@0 {
  474. compatible = "denx,u-boot-fdt-test";
  475. };
  476. };
  477. mmio-bus@1 {
  478. #address-cells = <1>;
  479. #size-cells = <1>;
  480. compatible = "denx,u-boot-test-bus";
  481. subnode@0 {
  482. compatible = "denx,u-boot-fdt-test";
  483. };
  484. };
  485. acpi_test1: acpi-test {
  486. compatible = "denx,u-boot-acpi-test";
  487. acpi-ssdt-test-data = "ab";
  488. acpi-dsdt-test-data = "hi";
  489. child {
  490. compatible = "denx,u-boot-acpi-test";
  491. };
  492. };
  493. acpi_test2: acpi-test2 {
  494. compatible = "denx,u-boot-acpi-test";
  495. acpi-ssdt-test-data = "cd";
  496. acpi-dsdt-test-data = "jk";
  497. };
  498. clocks {
  499. clk_fixed: clk-fixed {
  500. compatible = "fixed-clock";
  501. #clock-cells = <0>;
  502. clock-frequency = <1234>;
  503. };
  504. clk_fixed_factor: clk-fixed-factor {
  505. compatible = "fixed-factor-clock";
  506. #clock-cells = <0>;
  507. clock-div = <3>;
  508. clock-mult = <2>;
  509. clocks = <&clk_fixed>;
  510. };
  511. osc {
  512. compatible = "fixed-clock";
  513. #clock-cells = <0>;
  514. clock-frequency = <20000000>;
  515. };
  516. };
  517. clk_sandbox: clk-sbox {
  518. compatible = "sandbox,clk";
  519. #clock-cells = <1>;
  520. assigned-clocks = <&clk_sandbox 3>;
  521. assigned-clock-rates = <321>;
  522. };
  523. clk-test {
  524. compatible = "sandbox,clk-test";
  525. clocks = <&clk_fixed>,
  526. <&clk_sandbox 1>,
  527. <&clk_sandbox 0>,
  528. <&clk_sandbox 3>,
  529. <&clk_sandbox 2>;
  530. clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
  531. };
  532. ccf: clk-ccf {
  533. compatible = "sandbox,clk-ccf";
  534. };
  535. efi-media {
  536. compatible = "sandbox,efi-media";
  537. };
  538. eth@10002000 {
  539. compatible = "sandbox,eth";
  540. reg = <0x10002000 0x1000>;
  541. };
  542. eth_5: eth@10003000 {
  543. compatible = "sandbox,eth";
  544. reg = <0x10003000 0x1000>;
  545. nvmem-cells = <&eth5_addr>;
  546. nvmem-cell-names = "mac-address";
  547. };
  548. eth_3: sbe5 {
  549. compatible = "sandbox,eth";
  550. reg = <0x10005000 0x1000>;
  551. nvmem-cells = <&eth3_addr>;
  552. nvmem-cell-names = "mac-address";
  553. };
  554. eth@10004000 {
  555. compatible = "sandbox,eth";
  556. reg = <0x10004000 0x1000>;
  557. };
  558. phy_eth0: phy-test-eth {
  559. compatible = "sandbox,eth";
  560. reg = <0x10007000 0x1000>;
  561. mac-address = [ 02 00 11 22 33 49 ];
  562. phy-handle = <&ethphy1>;
  563. phy-mode = "2500base-x";
  564. };
  565. dsa_eth0: dsa-test-eth {
  566. compatible = "sandbox,eth";
  567. reg = <0x10006000 0x1000>;
  568. nvmem-cells = <&eth4_addr>;
  569. nvmem-cell-names = "mac-address";
  570. };
  571. dsa-test {
  572. compatible = "sandbox,dsa";
  573. ports {
  574. #address-cells = <1>;
  575. #size-cells = <0>;
  576. swp_0: port@0 {
  577. reg = <0>;
  578. label = "lan0";
  579. phy-mode = "rgmii-rxid";
  580. fixed-link {
  581. speed = <100>;
  582. full-duplex;
  583. };
  584. };
  585. swp_1: port@1 {
  586. reg = <1>;
  587. label = "lan1";
  588. phy-mode = "rgmii-txid";
  589. fixed-link = <0 1 100 0 0>;
  590. };
  591. port@2 {
  592. reg = <2>;
  593. ethernet = <&dsa_eth0>;
  594. fixed-link {
  595. speed = <1000>;
  596. full-duplex;
  597. };
  598. };
  599. };
  600. };
  601. firmware {
  602. sandbox_firmware: sandbox-firmware {
  603. compatible = "sandbox,firmware";
  604. };
  605. scmi {
  606. compatible = "sandbox,scmi-agent";
  607. #address-cells = <1>;
  608. #size-cells = <0>;
  609. protocol@10 {
  610. reg = <0x10>;
  611. };
  612. clk_scmi: protocol@14 {
  613. reg = <0x14>;
  614. #clock-cells = <1>;
  615. };
  616. reset_scmi: protocol@16 {
  617. reg = <0x16>;
  618. #reset-cells = <1>;
  619. };
  620. protocol@17 {
  621. reg = <0x17>;
  622. regulators {
  623. #address-cells = <1>;
  624. #size-cells = <0>;
  625. regul0_scmi: reg@0 {
  626. reg = <0>;
  627. regulator-name = "sandbox-voltd0";
  628. regulator-min-microvolt = <1100000>;
  629. regulator-max-microvolt = <3300000>;
  630. };
  631. regul1_scmi: reg@1 {
  632. reg = <0x1>;
  633. regulator-name = "sandbox-voltd1";
  634. regulator-min-microvolt = <1800000>;
  635. };
  636. };
  637. };
  638. };
  639. };
  640. fpga {
  641. compatible = "sandbox,fpga";
  642. };
  643. pinctrl-gpio {
  644. compatible = "sandbox,pinctrl-gpio";
  645. gpio_a: base-gpios {
  646. compatible = "sandbox,gpio";
  647. gpio-controller;
  648. #gpio-cells = <1>;
  649. gpio-bank-name = "a";
  650. sandbox,gpio-count = <20>;
  651. hog_input_active_low {
  652. gpio-hog;
  653. input;
  654. gpios = <10 GPIO_ACTIVE_LOW>;
  655. };
  656. hog_input_active_high {
  657. gpio-hog;
  658. input;
  659. gpios = <11 GPIO_ACTIVE_HIGH>;
  660. };
  661. hog_output_low {
  662. gpio-hog;
  663. output-low;
  664. gpios = <12 GPIO_ACTIVE_HIGH>;
  665. };
  666. hog_output_high {
  667. gpio-hog;
  668. output-high;
  669. gpios = <13 GPIO_ACTIVE_HIGH>;
  670. };
  671. };
  672. gpio_b: extra-gpios {
  673. compatible = "sandbox,gpio";
  674. gpio-controller;
  675. #gpio-cells = <5>;
  676. gpio-bank-name = "b";
  677. sandbox,gpio-count = <10>;
  678. };
  679. gpio_c: pinmux-gpios {
  680. compatible = "sandbox,gpio";
  681. gpio-controller;
  682. #gpio-cells = <2>;
  683. gpio-bank-name = "c";
  684. sandbox,gpio-count = <10>;
  685. };
  686. };
  687. i2c@0 {
  688. #address-cells = <1>;
  689. #size-cells = <0>;
  690. reg = <0 1>;
  691. compatible = "sandbox,i2c";
  692. clock-frequency = <100000>;
  693. pinctrl-names = "default";
  694. pinctrl-0 = <&pinmux_i2c0_pins>;
  695. eeprom@2c {
  696. #address-cells = <1>;
  697. #size-cells = <1>;
  698. reg = <0x2c>;
  699. compatible = "i2c-eeprom";
  700. sandbox,emul = <&emul_eeprom>;
  701. partitions {
  702. compatible = "fixed-partitions";
  703. #address-cells = <1>;
  704. #size-cells = <1>;
  705. bootcount_i2c: bootcount@10 {
  706. reg = <10 2>;
  707. };
  708. };
  709. eth3_addr: mac-address@24 {
  710. reg = <24 6>;
  711. };
  712. };
  713. rtc_0: rtc@43 {
  714. #address-cells = <1>;
  715. #size-cells = <1>;
  716. reg = <0x43>;
  717. compatible = "sandbox-rtc";
  718. sandbox,emul = <&emul0>;
  719. eth4_addr: mac-address@40 {
  720. reg = <0x40 6>;
  721. };
  722. };
  723. rtc_1: rtc@61 {
  724. reg = <0x61>;
  725. compatible = "sandbox-rtc";
  726. sandbox,emul = <&emul1>;
  727. };
  728. i2c_emul: emul {
  729. reg = <0xff>;
  730. compatible = "sandbox,i2c-emul-parent";
  731. emul_eeprom: emul-eeprom {
  732. compatible = "sandbox,i2c-eeprom";
  733. sandbox,filename = "i2c.bin";
  734. sandbox,size = <256>;
  735. };
  736. emul0: emul0 {
  737. compatible = "sandbox,i2c-rtc-emul";
  738. };
  739. emul1: emull {
  740. compatible = "sandbox,i2c-rtc-emul";
  741. };
  742. };
  743. sandbox_pmic: sandbox_pmic {
  744. reg = <0x40>;
  745. sandbox,emul = <&emul_pmic0>;
  746. };
  747. mc34708: pmic@41 {
  748. reg = <0x41>;
  749. sandbox,emul = <&emul_pmic1>;
  750. };
  751. };
  752. bootcount@0 {
  753. compatible = "u-boot,bootcount-rtc";
  754. rtc = <&rtc_1>;
  755. offset = <0x13>;
  756. };
  757. bootcount {
  758. compatible = "u-boot,bootcount-i2c-eeprom";
  759. i2c-eeprom = <&bootcount_i2c>;
  760. };
  761. bootcount_4@0 {
  762. compatible = "u-boot,bootcount-syscon";
  763. syscon = <&syscon0>;
  764. reg = <0x0 0x04>, <0x0 0x04>;
  765. reg-names = "syscon_reg", "offset";
  766. };
  767. bootcount_2@0 {
  768. compatible = "u-boot,bootcount-syscon";
  769. syscon = <&syscon0>;
  770. reg = <0x0 0x04>, <0x0 0x02> ;
  771. reg-names = "syscon_reg", "offset";
  772. };
  773. adc: adc@0 {
  774. compatible = "sandbox,adc";
  775. #io-channel-cells = <1>;
  776. vdd-supply = <&buck2>;
  777. vss-microvolts = <0>;
  778. };
  779. iommu: iommu@0 {
  780. compatible = "sandbox,iommu";
  781. #iommu-cells = <0>;
  782. };
  783. irq: irq {
  784. compatible = "sandbox,irq";
  785. interrupt-controller;
  786. #interrupt-cells = <2>;
  787. };
  788. lcd {
  789. bootph-all;
  790. compatible = "sandbox,lcd-sdl";
  791. pinctrl-names = "default";
  792. pinctrl-0 = <&pinmux_lcd_pins>;
  793. xres = <1366>;
  794. yres = <768>;
  795. };
  796. leds {
  797. compatible = "gpio-leds";
  798. iracibble {
  799. gpios = <&gpio_a 1 0>;
  800. label = "sandbox:red";
  801. };
  802. martinet {
  803. gpios = <&gpio_a 2 0>;
  804. label = "sandbox:green";
  805. };
  806. default_on {
  807. gpios = <&gpio_a 5 0>;
  808. label = "sandbox:default_on";
  809. default-state = "on";
  810. };
  811. default_off {
  812. gpios = <&gpio_a 6 0>;
  813. /* label intentionally omitted */
  814. default-state = "off";
  815. };
  816. };
  817. wdt-gpio-toggle {
  818. gpios = <&gpio_a 7 0>;
  819. compatible = "linux,wdt-gpio";
  820. hw_margin_ms = <100>;
  821. hw_algo = "toggle";
  822. always-running;
  823. };
  824. wdt-gpio-level {
  825. gpios = <&gpio_a 7 0>;
  826. compatible = "linux,wdt-gpio";
  827. hw_margin_ms = <100>;
  828. hw_algo = "level";
  829. always-running;
  830. };
  831. mbox: mbox {
  832. compatible = "sandbox,mbox";
  833. #mbox-cells = <1>;
  834. };
  835. mbox-test {
  836. compatible = "sandbox,mbox-test";
  837. mboxes = <&mbox 100>, <&mbox 1>;
  838. mbox-names = "other", "test";
  839. };
  840. cpus {
  841. #address-cells = <1>;
  842. #size-cells = <0>;
  843. timebase-frequency = <2000000>;
  844. cpu1: cpu@1 {
  845. device_type = "cpu";
  846. reg = <0x1>;
  847. timebase-frequency = <3000000>;
  848. compatible = "sandbox,cpu_sandbox";
  849. bootph-all;
  850. };
  851. cpu2: cpu@2 {
  852. device_type = "cpu";
  853. reg = <0x2>;
  854. compatible = "sandbox,cpu_sandbox";
  855. bootph-all;
  856. };
  857. cpu3: cpu@3 {
  858. device_type = "cpu";
  859. reg = <0x3>;
  860. compatible = "sandbox,cpu_sandbox";
  861. bootph-all;
  862. };
  863. };
  864. chipid: chipid {
  865. compatible = "sandbox,soc";
  866. };
  867. i2s: i2s {
  868. compatible = "sandbox,i2s";
  869. #sound-dai-cells = <1>;
  870. sandbox,silent; /* Don't emit sounds while testing */
  871. };
  872. nop-test_0 {
  873. compatible = "sandbox,nop_sandbox1";
  874. nop-test_1 {
  875. compatible = "sandbox,nop_sandbox2";
  876. bind = "True";
  877. };
  878. nop-test_2 {
  879. compatible = "sandbox,nop_sandbox2";
  880. bind = "False";
  881. };
  882. };
  883. memory-controller {
  884. compatible = "sandbox,memory";
  885. };
  886. misc-test {
  887. #address-cells = <1>;
  888. #size-cells = <1>;
  889. compatible = "sandbox,misc_sandbox";
  890. eth5_addr: mac-address@10 {
  891. reg = <0x10 6>;
  892. };
  893. };
  894. mmc2 {
  895. compatible = "sandbox,mmc";
  896. non-removable;
  897. };
  898. /* This is used for the bootdev tests */
  899. mmc1 {
  900. compatible = "sandbox,mmc";
  901. filename = "mmc1.img";
  902. };
  903. /* This is used for the fastboot tests */
  904. mmc0: mmc0 {
  905. compatible = "sandbox,mmc";
  906. };
  907. /* This is used for VBE VPL tests */
  908. mmc3 {
  909. status = "disabled";
  910. compatible = "sandbox,mmc";
  911. filename = "image.bin";
  912. non-removable;
  913. };
  914. /* This is used for bootstd bootmenu tests */
  915. mmc4 {
  916. status = "disabled";
  917. compatible = "sandbox,mmc";
  918. filename = "mmc4.img";
  919. };
  920. pch {
  921. compatible = "sandbox,pch";
  922. };
  923. pci0: pci@0 {
  924. compatible = "sandbox,pci";
  925. device_type = "pci";
  926. bus-range = <0x00 0xff>;
  927. #address-cells = <3>;
  928. #size-cells = <2>;
  929. ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
  930. 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
  931. iommu-map = <0x0010 &iommu 0 1>;
  932. iommu-map-mask = <0xfffffff8>;
  933. pci@0,0 {
  934. compatible = "pci-generic";
  935. reg = <0x0000 0 0 0 0>;
  936. sandbox,emul = <&swap_case_emul0_0>;
  937. };
  938. pci@1,0 {
  939. compatible = "pci-generic";
  940. /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
  941. reg = <0x02000814 0 0 0 0
  942. 0x01000810 0 0 0 0>;
  943. sandbox,emul = <&swap_case_emul0_1>;
  944. };
  945. p2sb-pci@2,0 {
  946. compatible = "sandbox,p2sb";
  947. reg = <0x02001010 0 0 0 0>;
  948. sandbox,emul = <&p2sb_emul>;
  949. adder {
  950. intel,p2sb-port-id = <3>;
  951. compatible = "sandbox,adder";
  952. };
  953. };
  954. pci@1e,0 {
  955. compatible = "sandbox,pmc";
  956. reg = <0xf000 0 0 0 0>;
  957. sandbox,emul = <&pmc_emul1e>;
  958. acpi-base = <0x400>;
  959. gpe0-dwx-mask = <0xf>;
  960. gpe0-dwx-shift-base = <4>;
  961. gpe0-dw = <6 7 9>;
  962. gpe0-sts = <0x20>;
  963. gpe0-en = <0x30>;
  964. };
  965. pci@1f,0 {
  966. compatible = "pci-generic";
  967. /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
  968. reg = <0x0100f810 0 0 0 0>;
  969. sandbox,emul = <&swap_case_emul0_1f>;
  970. };
  971. };
  972. pci-emul0 {
  973. compatible = "sandbox,pci-emul-parent";
  974. swap_case_emul0_0: emul0@0,0 {
  975. compatible = "sandbox,swap-case";
  976. };
  977. swap_case_emul0_1: emul0@1,0 {
  978. compatible = "sandbox,swap-case";
  979. use-ea;
  980. };
  981. swap_case_emul0_1f: emul0@1f,0 {
  982. compatible = "sandbox,swap-case";
  983. };
  984. p2sb_emul: emul@2,0 {
  985. compatible = "sandbox,p2sb-emul";
  986. };
  987. pmc_emul1e: emul@1e,0 {
  988. compatible = "sandbox,pmc-emul";
  989. };
  990. };
  991. pci1: pci@1 {
  992. compatible = "sandbox,pci";
  993. device_type = "pci";
  994. bus-range = <0x00 0xff>;
  995. #address-cells = <3>;
  996. #size-cells = <2>;
  997. ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
  998. 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
  999. 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
  1000. sandbox,dev-info = <0x08 0x00 0x1234 0x5678
  1001. 0x0c 0x00 0x1234 0x5678
  1002. 0x10 0x00 0x1234 0x5678>;
  1003. pci@10,0 {
  1004. reg = <0x8000 0 0 0 0>;
  1005. };
  1006. };
  1007. pci2: pci@2 {
  1008. compatible = "sandbox,pci";
  1009. device_type = "pci";
  1010. bus-range = <0x00 0xff>;
  1011. #address-cells = <3>;
  1012. #size-cells = <2>;
  1013. ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
  1014. 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
  1015. sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
  1016. pci@1f,0 {
  1017. compatible = "pci-generic";
  1018. reg = <0xf800 0 0 0 0>;
  1019. sandbox,emul = <&swap_case_emul2_1f>;
  1020. };
  1021. };
  1022. pci-emul2 {
  1023. compatible = "sandbox,pci-emul-parent";
  1024. swap_case_emul2_1f: emul2@1f,0 {
  1025. compatible = "sandbox,swap-case";
  1026. };
  1027. };
  1028. pci_ep: pci_ep {
  1029. compatible = "sandbox,pci_ep";
  1030. };
  1031. probing {
  1032. compatible = "simple-bus";
  1033. test1 {
  1034. compatible = "denx,u-boot-probe-test";
  1035. };
  1036. test2 {
  1037. compatible = "denx,u-boot-probe-test";
  1038. };
  1039. test3 {
  1040. compatible = "denx,u-boot-probe-test";
  1041. };
  1042. test4 {
  1043. compatible = "denx,u-boot-probe-test";
  1044. first-syscon = <&syscon0>;
  1045. second-sys-ctrl = <&another_system_controller>;
  1046. third-syscon = <&syscon2>;
  1047. };
  1048. };
  1049. pwrdom: power-domain {
  1050. compatible = "sandbox,power-domain";
  1051. #power-domain-cells = <1>;
  1052. };
  1053. power-domain-test {
  1054. compatible = "sandbox,power-domain-test";
  1055. power-domains = <&pwrdom 2>;
  1056. };
  1057. pwm: pwm {
  1058. compatible = "sandbox,pwm";
  1059. #pwm-cells = <2>;
  1060. pinctrl-names = "default";
  1061. pinctrl-0 = <&pinmux_pwm_pins>;
  1062. };
  1063. pwm2 {
  1064. compatible = "sandbox,pwm";
  1065. #pwm-cells = <2>;
  1066. };
  1067. ram {
  1068. compatible = "sandbox,ram";
  1069. };
  1070. reset@0 {
  1071. compatible = "sandbox,warm-reset";
  1072. bootph-some-ram;
  1073. };
  1074. reset@1 {
  1075. compatible = "sandbox,reset";
  1076. bootph-some-ram;
  1077. };
  1078. resetc: reset-ctl {
  1079. compatible = "sandbox,reset-ctl";
  1080. #reset-cells = <1>;
  1081. };
  1082. reset-ctl-test {
  1083. compatible = "sandbox,reset-ctl-test";
  1084. resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
  1085. reset-names = "other", "test", "test2", "test3";
  1086. };
  1087. rng {
  1088. compatible = "sandbox,sandbox-rng";
  1089. };
  1090. rproc_1: rproc@1 {
  1091. compatible = "sandbox,test-processor";
  1092. remoteproc-name = "remoteproc-test-dev1";
  1093. };
  1094. rproc_2: rproc@2 {
  1095. compatible = "sandbox,test-processor";
  1096. internal-memory-mapped;
  1097. remoteproc-name = "remoteproc-test-dev2";
  1098. };
  1099. panel {
  1100. compatible = "simple-panel";
  1101. backlight = <&backlight 0 100>;
  1102. };
  1103. scsi {
  1104. compatible = "sandbox,scsi";
  1105. sandbox,filepath = "scsi.img";
  1106. };
  1107. smem@0 {
  1108. compatible = "sandbox,smem";
  1109. };
  1110. sound {
  1111. compatible = "sandbox,sound";
  1112. cpu {
  1113. sound-dai = <&i2s 0>;
  1114. };
  1115. codec {
  1116. sound-dai = <&audio 0>;
  1117. };
  1118. };
  1119. spi@0 {
  1120. #address-cells = <1>;
  1121. #size-cells = <0>;
  1122. reg = <0 1>;
  1123. compatible = "sandbox,spi";
  1124. cs-gpios = <0>, <0>, <&gpio_a 0>;
  1125. pinctrl-names = "default";
  1126. pinctrl-0 = <&pinmux_spi0_pins>;
  1127. spi.bin@0 {
  1128. reg = <0>;
  1129. compatible = "spansion,m25p16", "jedec,spi-nor";
  1130. spi-max-frequency = <40000000>;
  1131. sandbox,filename = "spi.bin";
  1132. };
  1133. spi.bin@1 {
  1134. reg = <1>;
  1135. compatible = "spansion,m25p16", "jedec,spi-nor";
  1136. spi-max-frequency = <50000000>;
  1137. sandbox,filename = "spi.bin";
  1138. spi-cpol;
  1139. spi-cpha;
  1140. };
  1141. };
  1142. syscon0: syscon@0 {
  1143. compatible = "sandbox,syscon0";
  1144. reg = <0x10 16>;
  1145. };
  1146. another_system_controller: syscon@1 {
  1147. compatible = "sandbox,syscon1";
  1148. reg = <0x20 5
  1149. 0x28 6
  1150. 0x30 7
  1151. 0x38 8>;
  1152. };
  1153. syscon2: syscon@2 {
  1154. compatible = "simple-mfd", "syscon";
  1155. reg = <0x40 5
  1156. 0x48 6
  1157. 0x50 7
  1158. 0x58 8>;
  1159. };
  1160. syscon3: syscon@3 {
  1161. compatible = "simple-mfd", "syscon";
  1162. reg = <0x000100 0x10>;
  1163. muxcontroller0: a-mux-controller {
  1164. compatible = "mmio-mux";
  1165. #mux-control-cells = <1>;
  1166. mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
  1167. <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
  1168. <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
  1169. idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
  1170. u-boot,mux-autoprobe;
  1171. };
  1172. };
  1173. muxcontroller1: emul-mux-controller {
  1174. compatible = "mux-emul";
  1175. #mux-control-cells = <0>;
  1176. u-boot,mux-autoprobe;
  1177. idle-state = <0xabcd>;
  1178. };
  1179. testfdtm0 {
  1180. compatible = "denx,u-boot-fdtm-test";
  1181. };
  1182. testfdtm1: testfdtm1 {
  1183. compatible = "denx,u-boot-fdtm-test";
  1184. };
  1185. testfdtm2 {
  1186. compatible = "denx,u-boot-fdtm-test";
  1187. };
  1188. timer@0 {
  1189. compatible = "sandbox,timer";
  1190. clock-frequency = <1000000>;
  1191. };
  1192. timer@1 {
  1193. compatible = "sandbox,timer";
  1194. sandbox,timebase-frequency-fallback;
  1195. };
  1196. tpm2 {
  1197. compatible = "sandbox,tpm2";
  1198. };
  1199. tpm {
  1200. compatible = "google,sandbox-tpm";
  1201. };
  1202. uart0: serial {
  1203. compatible = "sandbox,serial";
  1204. bootph-all;
  1205. pinctrl-names = "default";
  1206. pinctrl-0 = <&pinmux_uart0_pins>;
  1207. };
  1208. usb_0: usb@0 {
  1209. compatible = "sandbox,usb";
  1210. status = "disabled";
  1211. hub {
  1212. compatible = "sandbox,usb-hub";
  1213. #address-cells = <1>;
  1214. #size-cells = <0>;
  1215. flash-stick {
  1216. reg = <0>;
  1217. compatible = "sandbox,usb-flash";
  1218. };
  1219. };
  1220. };
  1221. usb_1: usb@1 {
  1222. compatible = "sandbox,usb";
  1223. iommus = <&iommu>;
  1224. hub {
  1225. compatible = "usb-hub";
  1226. usb,device-class = <9>;
  1227. #address-cells = <1>;
  1228. #size-cells = <0>;
  1229. hub-emul {
  1230. compatible = "sandbox,usb-hub";
  1231. #address-cells = <1>;
  1232. #size-cells = <0>;
  1233. flash-stick@0 {
  1234. reg = <0>;
  1235. compatible = "sandbox,usb-flash";
  1236. sandbox,filepath = "testflash.bin";
  1237. };
  1238. flash-stick@1 {
  1239. reg = <1>;
  1240. compatible = "sandbox,usb-flash";
  1241. sandbox,filepath = "testflash1.bin";
  1242. };
  1243. flash-stick@2 {
  1244. reg = <2>;
  1245. compatible = "sandbox,usb-flash";
  1246. sandbox,filepath = "testflash2.bin";
  1247. };
  1248. keyb@3 {
  1249. reg = <3>;
  1250. compatible = "sandbox,usb-keyb";
  1251. };
  1252. };
  1253. usbstor@1 {
  1254. reg = <1>;
  1255. };
  1256. usbstor@3 {
  1257. reg = <3>;
  1258. };
  1259. };
  1260. };
  1261. usb_2: usb@2 {
  1262. compatible = "sandbox,usb";
  1263. status = "disabled";
  1264. };
  1265. spmi: spmi@0 {
  1266. compatible = "sandbox,spmi";
  1267. #address-cells = <0x1>;
  1268. #size-cells = <0x1>;
  1269. ranges;
  1270. pm8916@0 {
  1271. compatible = "qcom,spmi-pmic";
  1272. reg = <0x0 0x1>;
  1273. #address-cells = <0x1>;
  1274. #size-cells = <0x1>;
  1275. ranges;
  1276. spmi_gpios: gpios@c000 {
  1277. compatible = "qcom,pm8916-gpio";
  1278. reg = <0xc000 0x400>;
  1279. gpio-controller;
  1280. gpio-count = <4>;
  1281. #gpio-cells = <2>;
  1282. gpio-bank-name="spmi";
  1283. };
  1284. };
  1285. };
  1286. wdt0: wdt@0 {
  1287. compatible = "sandbox,wdt";
  1288. hw_margin_ms = <200>;
  1289. };
  1290. axi: axi@0 {
  1291. compatible = "sandbox,axi";
  1292. #address-cells = <0x1>;
  1293. #size-cells = <0x1>;
  1294. store@0 {
  1295. compatible = "sandbox,sandbox_store";
  1296. reg = <0x0 0x400>;
  1297. };
  1298. };
  1299. chosen {
  1300. #address-cells = <1>;
  1301. #size-cells = <1>;
  1302. setting = "sunrise ohoka";
  1303. other-node = "/some-bus/c-test@5";
  1304. int-values = <0x1937 72993>;
  1305. u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
  1306. chosen-test {
  1307. compatible = "denx,u-boot-fdt-test";
  1308. reg = <9 1>;
  1309. };
  1310. };
  1311. translation-test@8000 {
  1312. compatible = "simple-bus";
  1313. reg = <0x8000 0x4000>;
  1314. #address-cells = <0x2>;
  1315. #size-cells = <0x1>;
  1316. ranges = <0 0x0 0x8000 0x1000
  1317. 1 0x100 0x9000 0x1000
  1318. 2 0x200 0xA000 0x1000
  1319. 3 0x300 0xB000 0x1000
  1320. >;
  1321. dma-ranges = <0 0x000 0x10000000 0x1000
  1322. 1 0x100 0x20000000 0x1000
  1323. >;
  1324. dev@0,0 {
  1325. compatible = "denx,u-boot-fdt-dummy";
  1326. reg = <0 0x0 0x1000>;
  1327. reg-names = "sandbox-dummy-0";
  1328. };
  1329. dev@1,100 {
  1330. compatible = "denx,u-boot-fdt-dummy";
  1331. reg = <1 0x100 0x1000>;
  1332. };
  1333. dev@2,200 {
  1334. compatible = "denx,u-boot-fdt-dummy";
  1335. reg = <2 0x200 0x1000>;
  1336. };
  1337. noxlatebus@3,300 {
  1338. compatible = "simple-bus";
  1339. reg = <3 0x300 0x1000>;
  1340. #address-cells = <0x1>;
  1341. #size-cells = <0x0>;
  1342. dev@42 {
  1343. compatible = "denx,u-boot-fdt-dummy";
  1344. reg = <0x42>;
  1345. };
  1346. };
  1347. };
  1348. ofnode-foreach {
  1349. compatible = "foreach";
  1350. first {
  1351. prop1 = <1>;
  1352. prop2 = <2>;
  1353. };
  1354. second {
  1355. prop1 = <1>;
  1356. prop2 = <2>;
  1357. };
  1358. };
  1359. osd {
  1360. compatible = "sandbox,sandbox_osd";
  1361. };
  1362. sandbox_tee {
  1363. compatible = "sandbox,tee";
  1364. };
  1365. sandbox_virtio1 {
  1366. compatible = "sandbox,virtio1";
  1367. virtio-type = <4>; /* rng */
  1368. };
  1369. sandbox_virtio2 {
  1370. compatible = "sandbox,virtio2";
  1371. };
  1372. sandbox-virtio-blk {
  1373. compatible = "sandbox,virtio1";
  1374. virtio-type = <2>; /* block */
  1375. };
  1376. sandbox_scmi {
  1377. compatible = "sandbox,scmi-devices";
  1378. clocks = <&clk_scmi 2>, <&clk_scmi 0>;
  1379. resets = <&reset_scmi 3>;
  1380. regul0-supply = <&regul0_scmi>;
  1381. regul1-supply = <&regul1_scmi>;
  1382. };
  1383. pinctrl {
  1384. compatible = "sandbox,pinctrl";
  1385. pinctrl-names = "default", "alternate";
  1386. pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
  1387. pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
  1388. pinctrl_gpios: gpios {
  1389. gpio0 {
  1390. pins = "P5";
  1391. function = "GPIO";
  1392. bias-pull-up;
  1393. input-disable;
  1394. };
  1395. gpio1 {
  1396. pins = "P6";
  1397. function = "GPIO";
  1398. output-high;
  1399. drive-open-drain;
  1400. };
  1401. gpio2 {
  1402. pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
  1403. bias-pull-down;
  1404. input-enable;
  1405. };
  1406. gpio3 {
  1407. pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
  1408. bias-disable;
  1409. };
  1410. };
  1411. pinctrl_i2c: i2c {
  1412. groups {
  1413. groups = "I2C_UART";
  1414. function = "I2C";
  1415. };
  1416. pins {
  1417. pins = "P0", "P1";
  1418. drive-open-drain;
  1419. };
  1420. };
  1421. pinctrl_i2s: i2s {
  1422. groups = "SPI_I2S";
  1423. function = "I2S";
  1424. };
  1425. pinctrl_spi: spi {
  1426. groups = "SPI_I2S";
  1427. function = "SPI";
  1428. cs {
  1429. pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
  1430. <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
  1431. };
  1432. };
  1433. };
  1434. pinctrl-single-no-width {
  1435. compatible = "pinctrl-single";
  1436. reg = <0x0000 0x238>;
  1437. #pinctrl-cells = <1>;
  1438. pinctrl-single,function-mask = <0x7f>;
  1439. };
  1440. pinctrl-single-pins {
  1441. compatible = "pinctrl-single";
  1442. reg = <0x0000 0x238>;
  1443. #pinctrl-cells = <1>;
  1444. pinctrl-single,register-width = <32>;
  1445. pinctrl-single,function-mask = <0x7f>;
  1446. pinmux_pwm_pins: pinmux_pwm_pins {
  1447. pinctrl-single,pins = < 0x48 0x06 >;
  1448. };
  1449. pinmux_spi0_pins: pinmux_spi0_pins {
  1450. pinctrl-single,pins = <
  1451. 0x190 0x0c
  1452. 0x194 0x0c
  1453. 0x198 0x23
  1454. 0x19c 0x0c
  1455. >;
  1456. };
  1457. pinmux_uart0_pins: pinmux_uart0_pins {
  1458. pinctrl-single,pins = <
  1459. 0x70 0x30
  1460. 0x74 0x00
  1461. >;
  1462. };
  1463. };
  1464. pinctrl-single-bits {
  1465. compatible = "pinctrl-single";
  1466. reg = <0x0000 0x50>;
  1467. #pinctrl-cells = <2>;
  1468. pinctrl-single,bit-per-mux;
  1469. pinctrl-single,register-width = <32>;
  1470. pinctrl-single,function-mask = <0xf>;
  1471. pinmux_i2c0_pins: pinmux_i2c0_pins {
  1472. pinctrl-single,bits = <
  1473. 0x10 0x00002200 0x0000ff00
  1474. >;
  1475. };
  1476. pinmux_lcd_pins: pinmux_lcd_pins {
  1477. pinctrl-single,bits = <
  1478. 0x40 0x22222200 0xffffff00
  1479. 0x44 0x22222222 0xffffffff
  1480. 0x48 0x00000022 0x000000ff
  1481. 0x48 0x02000000 0x0f000000
  1482. 0x4c 0x02000022 0x0f0000ff
  1483. >;
  1484. };
  1485. };
  1486. hwspinlock@0 {
  1487. compatible = "sandbox,hwspinlock";
  1488. };
  1489. dma: dma {
  1490. compatible = "sandbox,dma";
  1491. #dma-cells = <1>;
  1492. dmas = <&dma 0>, <&dma 1>, <&dma 2>;
  1493. dma-names = "m2m", "tx0", "rx0";
  1494. };
  1495. /*
  1496. * keep mdio-mux ahead of mdio so that the mux is removed first at the
  1497. * end of the test. If parent mdio is removed first, clean-up of the
  1498. * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
  1499. * active at the end of the test. That it turn doesn't allow the mdio
  1500. * class to be destroyed, triggering an error.
  1501. */
  1502. mdio-mux-test {
  1503. compatible = "sandbox,mdio-mux";
  1504. #address-cells = <1>;
  1505. #size-cells = <0>;
  1506. mdio-parent-bus = <&mdio>;
  1507. mdio-ch-test@0 {
  1508. reg = <0>;
  1509. };
  1510. mdio-ch-test@1 {
  1511. reg = <1>;
  1512. };
  1513. };
  1514. mdio: mdio-test {
  1515. compatible = "sandbox,mdio";
  1516. #address-cells = <1>;
  1517. #size-cells = <0>;
  1518. ethphy1: ethernet-phy@1 {
  1519. reg = <1>;
  1520. };
  1521. };
  1522. pm-bus-test {
  1523. compatible = "simple-pm-bus";
  1524. clocks = <&clk_sandbox 4>;
  1525. power-domains = <&pwrdom 1>;
  1526. };
  1527. resetc2: syscon-reset {
  1528. compatible = "syscon-reset";
  1529. #reset-cells = <1>;
  1530. regmap = <&syscon0>;
  1531. offset = <1>;
  1532. mask = <0x27FFFFFF>;
  1533. assert-high = <0>;
  1534. };
  1535. syscon-reset-test {
  1536. compatible = "sandbox,misc_sandbox";
  1537. resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
  1538. reset-names = "valid", "no_mask", "out_of_range";
  1539. };
  1540. sysinfo {
  1541. compatible = "sandbox,sysinfo-sandbox";
  1542. };
  1543. sysinfo-gpio {
  1544. compatible = "gpio-sysinfo";
  1545. gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
  1546. revisions = <19>, <5>;
  1547. names = "rev_a", "foo";
  1548. };
  1549. some_regmapped-bus {
  1550. #address-cells = <0x1>;
  1551. #size-cells = <0x1>;
  1552. ranges = <0x0 0x0 0x10>;
  1553. compatible = "simple-bus";
  1554. regmap-test_0 {
  1555. reg = <0 0x10>;
  1556. compatible = "sandbox,regmap_test";
  1557. };
  1558. };
  1559. thermal {
  1560. compatible = "sandbox,thermal";
  1561. };
  1562. fwu-mdata {
  1563. compatible = "u-boot,fwu-mdata-gpt";
  1564. fwu-mdata-store = <&mmc0>;
  1565. };
  1566. nvmxip-qspi1@08000000 {
  1567. compatible = "nvmxip,qspi";
  1568. reg = <0x08000000 0x00200000>;
  1569. lba_shift = <9>;
  1570. lba = <4096>;
  1571. };
  1572. nvmxip-qspi2@08200000 {
  1573. compatible = "nvmxip,qspi";
  1574. reg = <0x08200000 0x00100000>;
  1575. lba_shift = <9>;
  1576. lba = <2048>;
  1577. };
  1578. extcon {
  1579. compatible = "sandbox,extcon";
  1580. };
  1581. arm-ffa-emul {
  1582. compatible = "sandbox,arm-ffa-emul";
  1583. sandbox-arm-ffa {
  1584. compatible = "sandbox,arm-ffa";
  1585. };
  1586. };
  1587. };
  1588. #include "sandbox_pmic.dtsi"
  1589. #include "cros-ec-keyboard.dtsi"
  1590. #ifdef CONFIG_SANDBOX_VPL
  1591. #include "sandbox_vpl.dtsi"
  1592. #endif
  1593. #include "cedit.dtsi"