Kconfig 22 KB

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  1. #
  2. # Multifunction miscellaneous devices
  3. #
  4. menu "Multifunction device drivers"
  5. config MISC
  6. bool "Enable Driver Model for Misc drivers"
  7. depends on DM
  8. help
  9. Enable driver model for miscellaneous devices. This class is
  10. used only for those do not fit other more general classes. A
  11. set of generic read, write and ioctl methods may be used to
  12. access the device.
  13. config SPL_MISC
  14. bool "Enable Driver Model for Misc drivers in SPL"
  15. depends on SPL_DM
  16. default MISC
  17. help
  18. Enable driver model for miscellaneous devices. This class is
  19. used only for those do not fit other more general classes. A
  20. set of generic read, write and ioctl methods may be used to
  21. access the device.
  22. config TPL_MISC
  23. bool "Enable Driver Model for Misc drivers in TPL"
  24. depends on TPL_DM
  25. default MISC
  26. help
  27. Enable driver model for miscellaneous devices. This class is
  28. used only for those do not fit other more general classes. A
  29. set of generic read, write and ioctl methods may be used to
  30. access the device.
  31. config VPL_MISC
  32. bool "Enable Driver Model for Misc drivers in VPL"
  33. depends on VPL_DM
  34. default MISC
  35. help
  36. Enable driver model for miscellaneous devices. This class is
  37. used only for those do not fit other more general classes. A
  38. set of generic read, write and ioctl methods may be used to
  39. access the device.
  40. config NVMEM
  41. bool "NVMEM support"
  42. help
  43. This adds support for a common interface to different types of
  44. non-volatile memory. Consumers can use nvmem-cells properties to look
  45. up hardware configuration data such as MAC addresses and calibration
  46. settings.
  47. config SPL_NVMEM
  48. bool "NVMEM support in SPL"
  49. help
  50. This adds support for a common interface to different types of
  51. non-volatile memory. Consumers can use nvmem-cells properties to look
  52. up hardware configuration data such as MAC addresses and calibration
  53. settings.
  54. config ALTERA_SYSID
  55. bool "Altera Sysid support"
  56. depends on MISC
  57. help
  58. Select this to enable a sysid for Altera devices. Please find
  59. details on the "Embedded Peripherals IP User Guide" of Altera.
  60. config ATSHA204A
  61. bool "Support for Atmel ATSHA204A module"
  62. select BITREVERSE
  63. depends on MISC
  64. help
  65. Enable support for I2C connected Atmel's ATSHA204A
  66. CryptoAuthentication module found for example on the Turris Omnia
  67. board.
  68. config GATEWORKS_SC
  69. bool "Gateworks System Controller Support"
  70. depends on MISC
  71. help
  72. Enable access for the Gateworks System Controller used on Gateworks
  73. boards to provide a boot watchdog, power control, temperature monitor,
  74. voltage ADCs, and EEPROM.
  75. config ROCKCHIP_EFUSE
  76. bool "Rockchip e-fuse support"
  77. depends on MISC
  78. help
  79. Enable (read-only) access for the e-fuse block found in Rockchip
  80. SoCs: accesses can either be made using byte addressing and a length
  81. or through child-nodes that are generated based on the e-fuse map
  82. retrieved from the DTS.
  83. config ROCKCHIP_OTP
  84. bool "Rockchip OTP Support"
  85. depends on MISC
  86. help
  87. Enable (read-only) access for the one-time-programmable memory block
  88. found in Rockchip SoCs: accesses can either be made using byte
  89. addressing and a length or through child-nodes that are generated
  90. based on the e-fuse map retrieved from the DTS.
  91. config SIFIVE_OTP
  92. bool "SiFive eMemory OTP driver"
  93. depends on MISC
  94. help
  95. Enable support for reading and writing the eMemory OTP on the
  96. SiFive SoCs.
  97. config SMSC_LPC47M
  98. bool "LPC47M SMSC driver"
  99. config SMSC_SIO1007
  100. bool "SIO1007 SMSC driver"
  101. config VEXPRESS_CONFIG
  102. bool "Enable support for Arm Versatile Express config bus"
  103. depends on MISC
  104. help
  105. If you say Y here, you will get support for accessing the
  106. configuration bus on the Arm Versatile Express boards via
  107. a sysreg driver.
  108. config CMD_CROS_EC
  109. bool "Enable crosec command"
  110. depends on CROS_EC
  111. help
  112. Enable command-line access to the Chrome OS EC (Embedded
  113. Controller). This provides the 'crosec' command which has
  114. a number of sub-commands for performing EC tasks such as
  115. updating its flash, accessing a small saved context area
  116. and talking to the I2C bus behind the EC (if there is one).
  117. config CROS_EC
  118. bool "Enable Chrome OS EC"
  119. help
  120. Enable access to the Chrome OS EC. This is a separate
  121. microcontroller typically available on a SPI bus on Chromebooks. It
  122. provides access to the keyboard, some internal storage and may
  123. control access to the battery and main PMIC depending on the
  124. device. You can use the 'crosec' command to access it.
  125. config SPL_CROS_EC
  126. bool "Enable Chrome OS EC in SPL"
  127. depends on SPL_MISC
  128. help
  129. Enable access to the Chrome OS EC in SPL. This is a separate
  130. microcontroller typically available on a SPI bus on Chromebooks. It
  131. provides access to the keyboard, some internal storage and may
  132. control access to the battery and main PMIC depending on the
  133. device. You can use the 'crosec' command to access it.
  134. config TPL_CROS_EC
  135. bool "Enable Chrome OS EC in TPL"
  136. depends on TPL_MISC
  137. help
  138. Enable access to the Chrome OS EC in TPL. This is a separate
  139. microcontroller typically available on a SPI bus on Chromebooks. It
  140. provides access to the keyboard, some internal storage and may
  141. control access to the battery and main PMIC depending on the
  142. device. You can use the 'crosec' command to access it.
  143. config VPL_CROS_EC
  144. bool "Enable Chrome OS EC in VPL"
  145. depends on VPL_MISC
  146. help
  147. Enable access to the Chrome OS EC in VPL. This is a separate
  148. microcontroller typically available on a SPI bus on Chromebooks. It
  149. provides access to the keyboard, some internal storage and may
  150. control access to the battery and main PMIC depending on the
  151. device. You can use the 'crosec' command to access it.
  152. config CROS_EC_I2C
  153. bool "Enable Chrome OS EC I2C driver"
  154. depends on CROS_EC
  155. help
  156. Enable I2C access to the Chrome OS EC. This is used on older
  157. ARM Chromebooks such as snow and spring before the standard bus
  158. changed to SPI. The EC will accept commands across the I2C using
  159. a special message protocol, and provide responses.
  160. config CROS_EC_LPC
  161. bool "Enable Chrome OS EC LPC driver"
  162. depends on CROS_EC
  163. help
  164. Enable I2C access to the Chrome OS EC. This is used on x86
  165. Chromebooks such as link and falco. The keyboard is provided
  166. through a legacy port interface, so on x86 machines the main
  167. function of the EC is power and thermal management.
  168. config SPL_CROS_EC_LPC
  169. bool "Enable Chrome OS EC LPC driver in SPL"
  170. depends on CROS_EC && SPL_MISC
  171. help
  172. Enable I2C access to the Chrome OS EC. This is used on x86
  173. Chromebooks such as link and falco. The keyboard is provided
  174. through a legacy port interface, so on x86 machines the main
  175. function of the EC is power and thermal management.
  176. config TPL_CROS_EC_LPC
  177. bool "Enable Chrome OS EC LPC driver in TPL"
  178. depends on CROS_EC && TPL_MISC
  179. help
  180. Enable I2C access to the Chrome OS EC. This is used on x86
  181. Chromebooks such as link and falco. The keyboard is provided
  182. through a legacy port interface, so on x86 machines the main
  183. function of the EC is power and thermal management.
  184. config VPL_CROS_EC_LPC
  185. bool "Enable Chrome OS EC LPC driver in VPL"
  186. depends on CROS_EC && VPL_MISC
  187. help
  188. Enable I2C access to the Chrome OS EC. This is used on x86
  189. Chromebooks such as link and falco. The keyboard is provided
  190. through a legacy port interface, so on x86 machines the main
  191. function of the EC is power and thermal management.
  192. config CROS_EC_SANDBOX
  193. bool "Enable Chrome OS EC sandbox driver"
  194. depends on CROS_EC && SANDBOX
  195. help
  196. Enable a sandbox emulation of the Chrome OS EC. This supports
  197. keyboard (use the -l flag to enable the LCD), verified boot context,
  198. EC flash read/write/erase support and a few other things. It is
  199. enough to perform a Chrome OS verified boot on sandbox.
  200. config SPL_CROS_EC_SANDBOX
  201. bool "Enable Chrome OS EC sandbox driver in SPL"
  202. depends on SPL_CROS_EC && SANDBOX
  203. help
  204. Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
  205. keyboard (use the -l flag to enable the LCD), verified boot context,
  206. EC flash read/write/erase support and a few other things. It is
  207. enough to perform a Chrome OS verified boot on sandbox.
  208. config TPL_CROS_EC_SANDBOX
  209. bool "Enable Chrome OS EC sandbox driver in TPL"
  210. depends on TPL_CROS_EC && SANDBOX
  211. help
  212. Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
  213. keyboard (use the -l flag to enable the LCD), verified boot context,
  214. EC flash read/write/erase support and a few other things. It is
  215. enough to perform a Chrome OS verified boot on sandbox.
  216. config VPL_CROS_EC_SANDBOX
  217. bool "Enable Chrome OS EC sandbox driver in VPL"
  218. depends on VPL_CROS_EC && SANDBOX
  219. help
  220. Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
  221. keyboard (use the -l flag to enable the LCD), verified boot context,
  222. EC flash read/write/erase support and a few other things. It is
  223. enough to perform a Chrome OS verified boot on sandbox.
  224. config CROS_EC_SPI
  225. bool "Enable Chrome OS EC SPI driver"
  226. depends on CROS_EC
  227. help
  228. Enable SPI access to the Chrome OS EC. This is used on newer
  229. ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
  230. provides a faster and more robust interface than I2C but the bugs
  231. are less interesting.
  232. config DS4510
  233. bool "Enable support for DS4510 CPU supervisor"
  234. help
  235. Enable support for the Maxim DS4510 CPU supervisor. It has an
  236. integrated 64-byte EEPROM, four programmable non-volatile I/O pins
  237. and a configurable timer for the supervisor function. The device is
  238. connected over I2C.
  239. config FSL_IIM
  240. bool "Enable FSL IC Identification Module (IIM) driver"
  241. depends on ARCH_MX31 || ARCH_MX5
  242. config FSL_SEC_MON
  243. bool "Enable FSL SEC_MON Driver"
  244. help
  245. Freescale Security Monitor block is responsible for monitoring
  246. system states.
  247. Security Monitor can be transitioned on any security failures,
  248. like software violations or hardware security violations.
  249. choice
  250. prompt "Security monitor interaction endianess"
  251. depends on FSL_SEC_MON
  252. default SYS_FSL_SEC_MON_BE if PPC
  253. default SYS_FSL_SEC_MON_LE
  254. config SYS_FSL_SEC_MON_LE
  255. bool "Security monitor interactions are little endian"
  256. config SYS_FSL_SEC_MON_BE
  257. bool "Security monitor interactions are big endian"
  258. endchoice
  259. config IRQ
  260. bool "Interrupt controller"
  261. help
  262. This enables support for interrupt controllers, including ITSS.
  263. Some devices have extra features, such as Apollo Lake. The
  264. device has its own uclass since there are several operations
  265. involved.
  266. config JZ4780_EFUSE
  267. bool "Ingenic JZ4780 eFUSE support"
  268. depends on ARCH_JZ47XX
  269. help
  270. This selects support for the eFUSE on Ingenic JZ4780 SoCs.
  271. config LS2_SFP
  272. bool "Layerscape Security Fuse Processor"
  273. depends on FSL_LSCH2 || ARCH_LS1021A
  274. depends on MISC
  275. imply DM_REGULATOR
  276. help
  277. This adds support for the Security Fuse Processor found on Layerscape
  278. SoCs. It contains various fuses related to secure boot, including the
  279. Super Root Key hash, One-Time-Programmable Master Key, Debug
  280. Challenge/Response values, and others. Fuses are numbered according
  281. to their four-byte offset from the start of the bank.
  282. If you don't need to read/program fuses, say 'n'.
  283. config MXC_OCOTP
  284. bool "Enable MXC OCOTP Driver"
  285. depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
  286. default y
  287. help
  288. If you say Y here, you will get support for the One Time
  289. Programmable memory pages that are stored on the some
  290. Freescale i.MX processors.
  291. config MXS_OCOTP
  292. bool "Enable MXS OCOTP Driver"
  293. depends on ARCH_MX23 || ARCH_MX28
  294. help
  295. If you say Y here, you will get support for the One Time
  296. Programmable memory pages that are stored on the
  297. Freescale i.MXS family of processors.
  298. config NPCM_HOST
  299. bool "Enable support espi or LPC for Host"
  300. depends on REGMAP && SYSCON
  301. help
  302. Enable NPCM BMC espi or LPC support for Host reading and writing.
  303. config SPL_MXC_OCOTP
  304. bool "Enable MXC OCOTP driver in SPL"
  305. depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
  306. default y
  307. help
  308. If you say Y here, you will get support for the One Time
  309. Programmable memory pages, that are stored on some
  310. Freescale i.MX processors, in SPL.
  311. config NPCM_OTP
  312. bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
  313. depends on (ARM && ARCH_NPCM)
  314. default n
  315. help
  316. Support NPCM BMC OTP memory (fuse).
  317. To compile this driver as a module, choose M here: the module
  318. will be called npcm_otp.
  319. config IMX_ELE
  320. bool "Enable i.MX EdgeLock Enclave MU driver and API"
  321. depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
  322. help
  323. If you say Y here to enable Message Unit driver to work with
  324. Sentinel core on some NXP i.MX processors.
  325. config NUVOTON_NCT6102D
  326. bool "Enable Nuvoton NCT6102D Super I/O driver"
  327. help
  328. If you say Y here, you will get support for the Nuvoton
  329. NCT6102D Super I/O driver. This can be used to enable or
  330. disable the legacy UART, the watchdog or other devices
  331. in the Nuvoton Super IO chips on X86 platforms.
  332. config P2SB
  333. bool "Intel Primary to Sideband Bridge"
  334. depends on X86 || SANDBOX
  335. help
  336. This enables support for the Intel Primary to Sideband Bridge,
  337. abbreviated to P2SB. The P2SB is used to access various peripherals
  338. such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
  339. space. The space is segmented into different channels and peripherals
  340. are accessed by device-specific means within those channels. Devices
  341. should be added in the device tree as subnodes of the P2SB. A
  342. Peripheral Channel Register? (PCR) API is provided to access those
  343. devices - see pcr_readl(), etc.
  344. config SPL_P2SB
  345. bool "Intel Primary to Sideband Bridge in SPL"
  346. depends on SPL_MISC && (X86 || SANDBOX)
  347. help
  348. The Primary to Sideband Bridge is used to access various peripherals
  349. through memory-mapped I/O in a large chunk of PCI space. The space is
  350. segmented into different channels and peripherals are accessed by
  351. device-specific means within those channels. Devices should be added
  352. in the device tree as subnodes of the p2sb.
  353. config TPL_P2SB
  354. bool "Intel Primary to Sideband Bridge in TPL"
  355. depends on TPL_MISC && (X86 || SANDBOX)
  356. help
  357. The Primary to Sideband Bridge is used to access various peripherals
  358. through memory-mapped I/O in a large chunk of PCI space. The space is
  359. segmented into different channels and peripherals are accessed by
  360. device-specific means within those channels. Devices should be added
  361. in the device tree as subnodes of the p2sb.
  362. config PWRSEQ
  363. bool "Enable power-sequencing drivers"
  364. depends on DM
  365. help
  366. Power-sequencing drivers provide support for controlling power for
  367. devices. They are typically referenced by a phandle from another
  368. device. When the device is started up, its power sequence can be
  369. initiated.
  370. config SPL_PWRSEQ
  371. bool "Enable power-sequencing drivers for SPL"
  372. depends on SPL_MISC && PWRSEQ
  373. help
  374. Power-sequencing drivers provide support for controlling power for
  375. devices. They are typically referenced by a phandle from another
  376. device. When the device is started up, its power sequence can be
  377. initiated.
  378. config PCA9551_LED
  379. bool "Enable PCA9551 LED driver"
  380. help
  381. Enable driver for PCA9551 LED controller. This controller
  382. is connected via I2C. So I2C needs to be enabled.
  383. config PCA9551_I2C_ADDR
  384. hex "I2C address of PCA9551 LED controller"
  385. depends on PCA9551_LED
  386. default 0x60
  387. help
  388. The I2C address of the PCA9551 LED controller.
  389. config STM32MP_FUSE
  390. bool "Enable STM32MP fuse wrapper providing the fuse API"
  391. depends on ARCH_STM32MP && MISC
  392. default y if CMD_FUSE
  393. help
  394. If you say Y here, you will get support for the fuse API (OTP)
  395. for STM32MP architecture.
  396. This API is needed for CMD_FUSE.
  397. config STM32_RCC
  398. bool "Enable RCC driver for the STM32 SoC's family"
  399. depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
  400. help
  401. Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
  402. block) is responsible of the management of the clock and reset
  403. generation.
  404. This driver is similar to an MFD driver in the Linux kernel.
  405. config TEGRA_CAR
  406. bool "Enable support for the Tegra CAR driver"
  407. depends on TEGRA_NO_BPMP
  408. help
  409. The Tegra CAR (Clock and Reset Controller) is a HW module that
  410. controls almost all clocks and resets in a Tegra SoC.
  411. config TEGRA186_BPMP
  412. bool "Enable support for the Tegra186 BPMP driver"
  413. depends on TEGRA186
  414. help
  415. The Tegra BPMP (Boot and Power Management Processor) is a separate
  416. auxiliary CPU embedded into Tegra to perform power management work,
  417. and controls related features such as clocks, resets, power domains,
  418. PMIC I2C bus, etc. This driver provides the core low-level
  419. communication path by which feature-specific drivers (such as clock)
  420. can make requests to the BPMP. This driver is similar to an MFD
  421. driver in the Linux kernel.
  422. config TEST_DRV
  423. bool "Enable support for test drivers"
  424. default y if SANDBOX
  425. help
  426. This enables drivers and uclasses that provides a way of testing the
  427. operations of memory allocation and driver/uclass methods in driver
  428. model. This should only be enabled for testing as it is not useful for
  429. anything else.
  430. config USB_HUB_USB251XB
  431. tristate "USB251XB Hub Controller Configuration Driver"
  432. depends on I2C
  433. help
  434. This option enables support for configuration via SMBus of the
  435. Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
  436. parameters may be set in devicetree or platform data.
  437. Say Y or M here if you need to configure such a device via SMBus.
  438. config TWL4030_LED
  439. bool "Enable TWL4030 LED controller"
  440. help
  441. Enable this to add support for the TWL4030 LED controller.
  442. config WINBOND_W83627
  443. bool "Enable Winbond Super I/O driver"
  444. help
  445. If you say Y here, you will get support for the Winbond
  446. W83627 Super I/O driver. This can be used to enable the
  447. legacy UART or other devices in the Winbond Super IO chips
  448. on X86 platforms.
  449. config QCOM_GENI_SE
  450. bool "Qualcomm GENI Serial Engine Driver"
  451. depends on ARCH_SNAPDRAGON
  452. help
  453. The driver manages Generic Interface (GENI) firmware based
  454. Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper.
  455. config QFW
  456. bool
  457. help
  458. Hidden option to enable QEMU fw_cfg interface and uclass. This will
  459. be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
  460. config QFW_PIO
  461. bool
  462. depends on QFW
  463. help
  464. Hidden option to enable PIO QEMU fw_cfg interface. This will be
  465. selected by the appropriate QEMU board.
  466. config QFW_MMIO
  467. bool
  468. depends on QFW
  469. help
  470. Hidden option to enable MMIO QEMU fw_cfg interface. This will be
  471. selected by the appropriate QEMU board.
  472. config I2C_EEPROM
  473. bool "Enable driver for generic I2C-attached EEPROMs"
  474. depends on MISC
  475. help
  476. Enable a generic driver for EEPROMs attached via I2C.
  477. config SPL_I2C_EEPROM
  478. bool "Enable driver for generic I2C-attached EEPROMs for SPL"
  479. depends on SPL_MISC
  480. help
  481. This option is an SPL-variant of the I2C_EEPROM option.
  482. See the help of I2C_EEPROM for details.
  483. config SYS_I2C_EEPROM_ADDR
  484. hex "Chip address of the EEPROM device"
  485. depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
  486. default 0
  487. if I2C_EEPROM
  488. config SYS_I2C_EEPROM_ADDR_OVERFLOW
  489. hex "EEPROM Address Overflow"
  490. default 0x0
  491. help
  492. EEPROM chips that implement "address overflow" are ones
  493. like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  494. address and the extra bits end up in the "chip address" bit
  495. slots. This makes a 24WC08 (1Kbyte) chip look like four 256
  496. byte chips.
  497. endif
  498. config GDSYS_RXAUI_CTRL
  499. bool "Enable gdsys RXAUI control driver"
  500. depends on MISC
  501. help
  502. Support gdsys FPGA's RXAUI control.
  503. config GDSYS_IOEP
  504. bool "Enable gdsys IOEP driver"
  505. depends on MISC
  506. help
  507. Support gdsys FPGA's IO endpoint driver.
  508. config MPC83XX_SERDES
  509. bool "Enable MPC83xx serdes driver"
  510. depends on MISC
  511. help
  512. Support for serdes found on MPC83xx SoCs.
  513. config FS_LOADER
  514. bool "Enable loader driver for file system"
  515. help
  516. This is file system generic loader which can be used to load
  517. the file image from the storage into target such as memory.
  518. The consumer driver would then use this loader to program whatever,
  519. ie. the FPGA device.
  520. config SPL_FS_LOADER
  521. bool "Enable loader driver for file system"
  522. depends on SPL
  523. help
  524. This is file system generic loader which can be used to load
  525. the file image from the storage into target such as memory.
  526. The consumer driver would then use this loader to program whatever,
  527. ie. the FPGA device.
  528. config GDSYS_SOC
  529. bool "Enable gdsys SOC driver"
  530. depends on MISC
  531. help
  532. Support for gdsys IHS SOC, a simple bus associated with each gdsys
  533. IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
  534. register maps are contained within the FPGA's register map.
  535. config IHS_FPGA
  536. bool "Enable IHS FPGA driver"
  537. depends on MISC
  538. help
  539. Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
  540. gdsys devices, which supply the majority of the functionality offered
  541. by the devices. This driver supports both CON and CPU variants of the
  542. devices, depending on the device tree entry.
  543. config ESM_K3
  544. bool "Enable K3 ESM driver"
  545. depends on ARCH_K3
  546. help
  547. Support ESM (Error Signaling Module) on TI K3 SoCs.
  548. config MICROCHIP_FLEXCOM
  549. bool "Enable Microchip Flexcom driver"
  550. depends on MISC
  551. help
  552. The Atmel Flexcom is just a wrapper which embeds a SPI controller,
  553. an I2C controller and an USART.
  554. Only one function can be used at a time and is chosen at boot time
  555. according to the device tree.
  556. config K3_AVS0
  557. depends on ARCH_K3 && SPL_DM_REGULATOR
  558. bool "AVS class 0 support for K3 devices"
  559. help
  560. K3 devices have the optimized voltage values for the main voltage
  561. domains stored in efuse within the VTM IP. This driver reads the
  562. optimized voltage from the efuse, so that it can be programmed
  563. to the PMIC on board.
  564. config ESM_PMIC
  565. bool "Enable PMIC ESM driver"
  566. depends on DM_PMIC
  567. help
  568. Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
  569. typically to reboot the board in error condition.
  570. config FSL_IFC
  571. bool
  572. config SL28CPLD
  573. bool "Enable Kontron sl28cpld multi-function driver"
  574. depends on DM_I2C
  575. help
  576. Support for the Kontron sl28cpld management controller. This is
  577. the base driver which provides common access methods for the
  578. sub-drivers.
  579. endmenu