abx80x.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * A driver for the I2C members of the Abracon AB x8xx RTC family,
  4. * and compatible: AB 1805 and AB 0805
  5. *
  6. * Copyright 2014-2015 Macq S.A.
  7. * Copyright 2020 Linaro
  8. *
  9. * Author: Philippe De Muyter <phdm@macqel.be>
  10. * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
  11. * Author: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
  12. *
  13. */
  14. #include <common.h>
  15. #include <dm.h>
  16. #include <i2c.h>
  17. #include <rtc.h>
  18. #include <log.h>
  19. #include <linux/bitfield.h>
  20. #define ABX8XX_REG_HTH 0x00
  21. #define ABX8XX_REG_SC 0x01
  22. #define ABX8XX_REG_MN 0x02
  23. #define ABX8XX_REG_HR 0x03
  24. #define ABX8XX_REG_DA 0x04
  25. #define ABX8XX_REG_MO 0x05
  26. #define ABX8XX_REG_YR 0x06
  27. #define ABX8XX_REG_WD 0x07
  28. #define ABX8XX_REG_AHTH 0x08
  29. #define ABX8XX_REG_ASC 0x09
  30. #define ABX8XX_REG_AMN 0x0a
  31. #define ABX8XX_REG_AHR 0x0b
  32. #define ABX8XX_REG_ADA 0x0c
  33. #define ABX8XX_REG_AMO 0x0d
  34. #define ABX8XX_REG_AWD 0x0e
  35. #define ABX8XX_REG_STATUS 0x0f
  36. #define ABX8XX_STATUS_AF BIT(2)
  37. #define ABX8XX_STATUS_BLF BIT(4)
  38. #define ABX8XX_STATUS_WDT BIT(6)
  39. #define ABX8XX_REG_CTRL1 0x10
  40. #define ABX8XX_CTRL_WRITE BIT(0)
  41. #define ABX8XX_CTRL_ARST BIT(2)
  42. #define ABX8XX_CTRL_12_24 BIT(6)
  43. #define ABX8XX_REG_CTRL2 0x11
  44. #define ABX8XX_CTRL2_RSVD BIT(5)
  45. #define ABX8XX_REG_IRQ 0x12
  46. #define ABX8XX_IRQ_AIE BIT(2)
  47. #define ABX8XX_IRQ_IM_1_4 (0x3 << 5)
  48. #define ABX8XX_REG_CD_TIMER_CTL 0x18
  49. #define ABX8XX_REG_OSC 0x1c
  50. #define ABX8XX_OSC_FOS BIT(3)
  51. #define ABX8XX_OSC_BOS BIT(4)
  52. #define ABX8XX_OSC_ACAL_512 BIT(5)
  53. #define ABX8XX_OSC_ACAL_1024 BIT(6)
  54. #define ABX8XX_OSC_OSEL BIT(7)
  55. #define ABX8XX_REG_OSS 0x1d
  56. #define ABX8XX_OSS_OF BIT(1)
  57. #define ABX8XX_OSS_OMODE BIT(4)
  58. #define ABX8XX_REG_WDT 0x1b
  59. #define ABX8XX_WDT_WDS BIT(7)
  60. #define ABX8XX_WDT_BMB_MASK 0x7c
  61. #define ABX8XX_WDT_BMB_SHIFT 2
  62. #define ABX8XX_WDT_MAX_TIME (ABX8XX_WDT_BMB_MASK >> ABX8XX_WDT_BMB_SHIFT)
  63. #define ABX8XX_WDT_WRB_MASK 0x03
  64. #define ABX8XX_WDT_WRB_1HZ 0x02
  65. #define ABX8XX_REG_CFG_KEY 0x1f
  66. #define ABX8XX_CFG_KEY_OSC 0xa1
  67. #define ABX8XX_CFG_KEY_MISC 0x9d
  68. #define ABX8XX_REG_ID0 0x28
  69. #define ABX8XX_REG_OUT_CTRL 0x30
  70. #define ABX8XX_OUT_CTRL_EXDS BIT(4)
  71. #define ABX8XX_REG_TRICKLE 0x20
  72. #define ABX8XX_TRICKLE_CHARGE_ENABLE 0xa0
  73. #define ABX8XX_TRICKLE_STANDARD_DIODE 0x8
  74. #define ABX8XX_TRICKLE_SCHOTTKY_DIODE 0x4
  75. #define ABX8XX_REG_EXTRAM 0x3f
  76. #define ABX8XX_EXTRAM_XADS GENMASK(1, 0)
  77. #define ABX8XX_SRAM_BASE 0x40
  78. #define ABX8XX_SRAM_WIN_SIZE 0x40U
  79. #define ABX8XX_RAM_SIZE 256
  80. #define RAM_ADDR_LOWER GENMASK(5, 0)
  81. #define RAM_ADDR_UPPER GENMASK(7, 6)
  82. static u8 trickle_resistors[] = {0, 3, 6, 11};
  83. enum abx80x_chip {AB0801, AB0803, AB0804, AB0805,
  84. AB1801, AB1803, AB1804, AB1805, RV1805, ABX80X};
  85. struct abx80x_cap {
  86. u16 pn;
  87. bool has_tc;
  88. bool has_wdog;
  89. };
  90. static struct abx80x_cap abx80x_caps[] = {
  91. [AB0801] = {.pn = 0x0801},
  92. [AB0803] = {.pn = 0x0803},
  93. [AB0804] = {.pn = 0x0804, .has_tc = true, .has_wdog = true},
  94. [AB0805] = {.pn = 0x0805, .has_tc = true, .has_wdog = true},
  95. [AB1801] = {.pn = 0x1801},
  96. [AB1803] = {.pn = 0x1803},
  97. [AB1804] = {.pn = 0x1804, .has_tc = true, .has_wdog = true},
  98. [AB1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
  99. [RV1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
  100. [ABX80X] = {.pn = 0}
  101. };
  102. static int abx80x_rtc_xfer(struct udevice *dev, unsigned int offset,
  103. u8 *val, unsigned int bytes, bool write)
  104. {
  105. int ret;
  106. if (offset + bytes > ABX8XX_RAM_SIZE)
  107. return -EINVAL;
  108. while (bytes) {
  109. u8 extram, reg, len, lower, upper;
  110. lower = FIELD_GET(RAM_ADDR_LOWER, offset);
  111. upper = FIELD_GET(RAM_ADDR_UPPER, offset);
  112. extram = FIELD_PREP(ABX8XX_EXTRAM_XADS, upper);
  113. reg = ABX8XX_SRAM_BASE + lower;
  114. len = min(lower + bytes, ABX8XX_SRAM_WIN_SIZE) - lower;
  115. ret = dm_i2c_reg_write(dev, ABX8XX_REG_EXTRAM, extram);
  116. if (ret)
  117. return ret;
  118. if (write)
  119. ret = dm_i2c_write(dev, reg, val, len);
  120. else
  121. ret = dm_i2c_read(dev, reg, val, len);
  122. if (ret)
  123. return ret;
  124. offset += len;
  125. val += len;
  126. bytes -= len;
  127. }
  128. return 0;
  129. }
  130. static int abx80x_rtc_read(struct udevice *dev, unsigned int offset, u8 *val,
  131. unsigned int bytes)
  132. {
  133. return abx80x_rtc_xfer(dev, offset, val, bytes, false);
  134. }
  135. static int abx80x_rtc_write(struct udevice *dev, unsigned int offset,
  136. const u8 *val, unsigned int bytes)
  137. {
  138. return abx80x_rtc_xfer(dev, offset, (u8 *)val, bytes, true);
  139. }
  140. static int abx80x_is_rc_mode(struct udevice *dev)
  141. {
  142. int flags = 0;
  143. flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS);
  144. if (flags < 0) {
  145. log_err("Failed to read autocalibration attribute\n");
  146. return flags;
  147. }
  148. return (flags & ABX8XX_OSS_OMODE) ? 1 : 0;
  149. }
  150. static int abx80x_enable_trickle_charger(struct udevice *dev, u8 trickle_cfg)
  151. {
  152. int err;
  153. /*
  154. * Write the configuration key register to enable access to the Trickle
  155. * register
  156. */
  157. err = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY, ABX8XX_CFG_KEY_MISC);
  158. if (err < 0) {
  159. log_err("Unable to write configuration key\n");
  160. return -EIO;
  161. }
  162. err = dm_i2c_reg_write(dev, ABX8XX_REG_TRICKLE,
  163. ABX8XX_TRICKLE_CHARGE_ENABLE | trickle_cfg);
  164. if (err < 0) {
  165. log_err("Unable to write trickle register\n");
  166. return -EIO;
  167. }
  168. return 0;
  169. }
  170. static int abx80x_rtc_read_time(struct udevice *dev, struct rtc_time *tm)
  171. {
  172. unsigned char buf[8];
  173. int err, flags, rc_mode = 0;
  174. /* Read the Oscillator Failure only in XT mode */
  175. rc_mode = abx80x_is_rc_mode(dev);
  176. if (rc_mode < 0)
  177. return rc_mode;
  178. if (!rc_mode) {
  179. flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS);
  180. if (flags < 0) {
  181. log_err("Unable to read oscillator status.\n");
  182. return flags;
  183. }
  184. if (flags & ABX8XX_OSS_OF)
  185. log_debug("Oscillator fail, data is not accurate.\n");
  186. }
  187. err = dm_i2c_read(dev, ABX8XX_REG_HTH,
  188. buf, sizeof(buf));
  189. if (err < 0) {
  190. log_err("Unable to read date\n");
  191. return -EIO;
  192. }
  193. tm->tm_sec = bcd2bin(buf[ABX8XX_REG_SC] & 0x7F);
  194. tm->tm_min = bcd2bin(buf[ABX8XX_REG_MN] & 0x7F);
  195. tm->tm_hour = bcd2bin(buf[ABX8XX_REG_HR] & 0x3F);
  196. tm->tm_wday = buf[ABX8XX_REG_WD] & 0x7;
  197. tm->tm_mday = bcd2bin(buf[ABX8XX_REG_DA] & 0x3F);
  198. tm->tm_mon = bcd2bin(buf[ABX8XX_REG_MO] & 0x1F);
  199. tm->tm_year = bcd2bin(buf[ABX8XX_REG_YR]) + 2000;
  200. return 0;
  201. }
  202. static int abx80x_rtc_set_time(struct udevice *dev, const struct rtc_time *tm)
  203. {
  204. unsigned char buf[8];
  205. int err, flags;
  206. if (tm->tm_year < 2000)
  207. return -EINVAL;
  208. buf[ABX8XX_REG_HTH] = 0;
  209. buf[ABX8XX_REG_SC] = bin2bcd(tm->tm_sec);
  210. buf[ABX8XX_REG_MN] = bin2bcd(tm->tm_min);
  211. buf[ABX8XX_REG_HR] = bin2bcd(tm->tm_hour);
  212. buf[ABX8XX_REG_DA] = bin2bcd(tm->tm_mday);
  213. buf[ABX8XX_REG_MO] = bin2bcd(tm->tm_mon);
  214. buf[ABX8XX_REG_YR] = bin2bcd(tm->tm_year - 2000);
  215. buf[ABX8XX_REG_WD] = tm->tm_wday;
  216. err = dm_i2c_write(dev, ABX8XX_REG_HTH,
  217. buf, sizeof(buf));
  218. if (err < 0) {
  219. log_err("Unable to write to date registers\n");
  220. return -EIO;
  221. }
  222. /* Clear the OF bit of Oscillator Status Register */
  223. flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSS);
  224. if (flags < 0) {
  225. log_err("Unable to read oscillator status.\n");
  226. return flags;
  227. }
  228. err = dm_i2c_reg_write(dev, ABX8XX_REG_OSS,
  229. flags & ~ABX8XX_OSS_OF);
  230. if (err < 0) {
  231. log_err("Unable to write oscillator status register\n");
  232. return err;
  233. }
  234. return 0;
  235. }
  236. static int abx80x_rtc_set_autocalibration(struct udevice *dev,
  237. int autocalibration)
  238. {
  239. int retval, flags = 0;
  240. if (autocalibration != 0 && autocalibration != 1024 &&
  241. autocalibration != 512) {
  242. log_err("autocalibration value outside permitted range\n");
  243. return -EINVAL;
  244. }
  245. flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSC);
  246. if (flags < 0)
  247. return flags;
  248. if (autocalibration == 0) {
  249. flags &= ~(ABX8XX_OSC_ACAL_512 | ABX8XX_OSC_ACAL_1024);
  250. } else if (autocalibration == 1024) {
  251. /* 1024 autocalibration is 0x10 */
  252. flags |= ABX8XX_OSC_ACAL_1024;
  253. flags &= ~(ABX8XX_OSC_ACAL_512);
  254. } else {
  255. /* 512 autocalibration is 0x11 */
  256. flags |= (ABX8XX_OSC_ACAL_1024 | ABX8XX_OSC_ACAL_512);
  257. }
  258. /* Unlock write access to Oscillator Control Register */
  259. retval = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY,
  260. ABX8XX_CFG_KEY_OSC);
  261. if (retval < 0) {
  262. log_err("Failed to write CONFIG_KEY register\n");
  263. return retval;
  264. }
  265. retval = dm_i2c_reg_write(dev, ABX8XX_REG_OSC, flags);
  266. return retval;
  267. }
  268. static int abx80x_rtc_get_autocalibration(struct udevice *dev)
  269. {
  270. int flags = 0, autocalibration;
  271. flags = dm_i2c_reg_read(dev, ABX8XX_REG_OSC);
  272. if (flags < 0)
  273. return flags;
  274. if (flags & ABX8XX_OSC_ACAL_512)
  275. autocalibration = 512;
  276. else if (flags & ABX8XX_OSC_ACAL_1024)
  277. autocalibration = 1024;
  278. else
  279. autocalibration = 0;
  280. return autocalibration;
  281. }
  282. static struct rtc_time default_tm = { 0, 0, 0, 1, 1, 2000, 6, 0, 0 };
  283. static int abx80x_rtc_reset(struct udevice *dev)
  284. {
  285. int ret = 0;
  286. int autocalib = abx80x_rtc_get_autocalibration(dev);
  287. if (autocalib != 0)
  288. abx80x_rtc_set_autocalibration(dev, 0);
  289. ret = abx80x_rtc_set_time(dev, &default_tm);
  290. if (ret != 0) {
  291. log_err("cannot set time to default_tm. error %d\n", ret);
  292. return ret;
  293. }
  294. return ret;
  295. }
  296. static const struct rtc_ops abx80x_rtc_ops = {
  297. .get = abx80x_rtc_read_time,
  298. .set = abx80x_rtc_set_time,
  299. .reset = abx80x_rtc_reset,
  300. .read = abx80x_rtc_read,
  301. .write = abx80x_rtc_write,
  302. };
  303. static int abx80x_dt_trickle_cfg(struct udevice *dev)
  304. {
  305. const char *diode;
  306. int trickle_cfg = 0;
  307. int i, ret = 0;
  308. u32 tmp;
  309. diode = ofnode_read_string(dev_ofnode(dev), "abracon,tc-diode");
  310. if (!diode)
  311. return ret;
  312. if (!strcmp(diode, "standard")) {
  313. trickle_cfg |= ABX8XX_TRICKLE_STANDARD_DIODE;
  314. } else if (!strcmp(diode, "schottky")) {
  315. trickle_cfg |= ABX8XX_TRICKLE_SCHOTTKY_DIODE;
  316. } else {
  317. log_err("Invalid tc-diode value: %s\n", diode);
  318. return -EINVAL;
  319. }
  320. ret = ofnode_read_u32(dev_ofnode(dev), "abracon,tc-resistor", &tmp);
  321. if (ret)
  322. return ret;
  323. for (i = 0; i < sizeof(trickle_resistors); i++)
  324. if (trickle_resistors[i] == tmp)
  325. break;
  326. if (i == sizeof(trickle_resistors)) {
  327. log_err("Invalid tc-resistor value: %u\n", tmp);
  328. return -EINVAL;
  329. }
  330. return (trickle_cfg | i);
  331. }
  332. static int abx80x_probe(struct udevice *dev)
  333. {
  334. int i, data, err, trickle_cfg = -EINVAL;
  335. unsigned char buf[7];
  336. unsigned int part = dev->driver_data;
  337. unsigned int partnumber;
  338. unsigned int majrev, minrev;
  339. unsigned int lot;
  340. unsigned int wafer;
  341. unsigned int uid;
  342. err = dm_i2c_read(dev, ABX8XX_REG_ID0, buf, sizeof(buf));
  343. if (err < 0) {
  344. log_err("Unable to read partnumber\n");
  345. return -EIO;
  346. }
  347. partnumber = (buf[0] << 8) | buf[1];
  348. majrev = buf[2] >> 3;
  349. minrev = buf[2] & 0x7;
  350. lot = ((buf[4] & 0x80) << 2) | ((buf[6] & 0x80) << 1) | buf[3];
  351. uid = ((buf[4] & 0x7f) << 8) | buf[5];
  352. wafer = (buf[6] & 0x7c) >> 2;
  353. log_debug("model %04x, revision %u.%u, lot %x, wafer %x, uid %x\n",
  354. partnumber, majrev, minrev, lot, wafer, uid);
  355. data = dm_i2c_reg_read(dev, ABX8XX_REG_CTRL1);
  356. if (data < 0) {
  357. log_err("Unable to read control register\n");
  358. return -EIO;
  359. }
  360. err = dm_i2c_reg_write(dev, ABX8XX_REG_CTRL1,
  361. ((data & ~(ABX8XX_CTRL_12_24 |
  362. ABX8XX_CTRL_ARST)) |
  363. ABX8XX_CTRL_WRITE));
  364. if (err < 0) {
  365. log_err("Unable to write control register\n");
  366. return -EIO;
  367. }
  368. /* Configure RV1805 specifics */
  369. if (part == RV1805) {
  370. /*
  371. * Avoid accidentally entering test mode. This can happen
  372. * on the RV1805 in case the reserved bit 5 in control2
  373. * register is set. RV-1805-C3 datasheet indicates that
  374. * the bit should be cleared in section 11h - Control2.
  375. */
  376. data = dm_i2c_reg_read(dev, ABX8XX_REG_CTRL2);
  377. if (data < 0) {
  378. log_err("Unable to read control2 register\n");
  379. return -EIO;
  380. }
  381. err = dm_i2c_reg_write(dev, ABX8XX_REG_CTRL2,
  382. data & ~ABX8XX_CTRL2_RSVD);
  383. if (err < 0) {
  384. log_err("Unable to write control2 register\n");
  385. return -EIO;
  386. }
  387. /*
  388. * Avoid extra power leakage. The RV1805 uses smaller
  389. * 10pin package and the EXTI input is not present.
  390. * Disable it to avoid leakage.
  391. */
  392. data = dm_i2c_reg_read(dev, ABX8XX_REG_OUT_CTRL);
  393. if (data < 0) {
  394. log_err("Unable to read output control register\n");
  395. return -EIO;
  396. }
  397. /*
  398. * Write the configuration key register to enable access to
  399. * the config2 register
  400. */
  401. err = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY,
  402. ABX8XX_CFG_KEY_MISC);
  403. if (err < 0) {
  404. log_err("Unable to write configuration key\n");
  405. return -EIO;
  406. }
  407. err = dm_i2c_reg_write(dev, ABX8XX_REG_OUT_CTRL,
  408. data | ABX8XX_OUT_CTRL_EXDS);
  409. if (err < 0) {
  410. log_err("Unable to write output control register\n");
  411. return -EIO;
  412. }
  413. }
  414. /* part autodetection */
  415. if (part == ABX80X) {
  416. for (i = 0; abx80x_caps[i].pn; i++)
  417. if (partnumber == abx80x_caps[i].pn)
  418. break;
  419. if (abx80x_caps[i].pn == 0) {
  420. log_err("Unknown part: %04x\n", partnumber);
  421. return -EINVAL;
  422. }
  423. part = i;
  424. }
  425. if (partnumber != abx80x_caps[part].pn) {
  426. log_err("partnumber mismatch %04x != %04x\n",
  427. partnumber, abx80x_caps[part].pn);
  428. return -EINVAL;
  429. }
  430. if (abx80x_caps[part].has_tc)
  431. trickle_cfg = abx80x_dt_trickle_cfg(dev);
  432. if (trickle_cfg > 0) {
  433. log_debug("Enabling trickle charger: %02x\n", trickle_cfg);
  434. abx80x_enable_trickle_charger(dev, trickle_cfg);
  435. }
  436. err = dm_i2c_reg_write(dev, ABX8XX_REG_CD_TIMER_CTL, BIT(2));
  437. if (err)
  438. return err;
  439. return 0;
  440. }
  441. static const struct udevice_id abx80x_of_match[] = {
  442. {
  443. .compatible = "abracon,abx80x",
  444. .data = ABX80X
  445. },
  446. {
  447. .compatible = "abracon,ab0801",
  448. .data = AB0801
  449. },
  450. {
  451. .compatible = "abracon,ab0803",
  452. .data = AB0803
  453. },
  454. {
  455. .compatible = "abracon,ab0804",
  456. .data = AB0804
  457. },
  458. {
  459. .compatible = "abracon,ab0805",
  460. .data = AB0805
  461. },
  462. {
  463. .compatible = "abracon,ab1801",
  464. .data = AB1801
  465. },
  466. {
  467. .compatible = "abracon,ab1803",
  468. .data = AB1803
  469. },
  470. {
  471. .compatible = "abracon,ab1804",
  472. .data = AB1804
  473. },
  474. {
  475. .compatible = "abracon,ab1805",
  476. .data = AB1805
  477. },
  478. {
  479. .compatible = "microcrystal,rv1805",
  480. .data = RV1805
  481. },
  482. { }
  483. };
  484. U_BOOT_DRIVER(abx80x_rtc) = {
  485. .name = "rtc-abx80x",
  486. .id = UCLASS_RTC,
  487. .probe = abx80x_probe,
  488. .of_match = abx80x_of_match,
  489. .ops = &abx80x_rtc_ops,
  490. };