altera_timer.c 2.2 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
  7. * Scott McNutt <smcnutt@psyent.com>
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <timer.h>
  13. #include <asm/io.h>
  14. #include <linux/bitops.h>
  15. /* control register */
  16. #define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */
  17. #define ALTERA_TIMER_START BIT(2) /* Start timer */
  18. #define ALTERA_TIMER_STOP BIT(3) /* Stop timer */
  19. struct altera_timer_regs {
  20. u32 status; /* Timer status reg */
  21. u32 control; /* Timer control reg */
  22. u32 periodl; /* Timeout period low */
  23. u32 periodh; /* Timeout period high */
  24. u32 snapl; /* Snapshot low */
  25. u32 snaph; /* Snapshot high */
  26. };
  27. struct altera_timer_plat {
  28. struct altera_timer_regs *regs;
  29. };
  30. static u64 altera_timer_get_count(struct udevice *dev)
  31. {
  32. struct altera_timer_plat *plat = dev_get_plat(dev);
  33. struct altera_timer_regs *const regs = plat->regs;
  34. u32 val;
  35. /* Trigger update */
  36. writel(0x0, &regs->snapl);
  37. /* Read timer value */
  38. val = readl(&regs->snapl) & 0xffff;
  39. val |= (readl(&regs->snaph) & 0xffff) << 16;
  40. return timer_conv_64(~val);
  41. }
  42. static int altera_timer_probe(struct udevice *dev)
  43. {
  44. struct altera_timer_plat *plat = dev_get_plat(dev);
  45. struct altera_timer_regs *const regs = plat->regs;
  46. writel(0, &regs->status);
  47. writel(0, &regs->control);
  48. writel(ALTERA_TIMER_STOP, &regs->control);
  49. writel(0xffff, &regs->periodl);
  50. writel(0xffff, &regs->periodh);
  51. writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, &regs->control);
  52. return 0;
  53. }
  54. static int altera_timer_of_to_plat(struct udevice *dev)
  55. {
  56. struct altera_timer_plat *plat = dev_get_plat(dev);
  57. plat->regs = map_physmem(dev_read_addr(dev),
  58. sizeof(struct altera_timer_regs),
  59. MAP_NOCACHE);
  60. return 0;
  61. }
  62. static const struct timer_ops altera_timer_ops = {
  63. .get_count = altera_timer_get_count,
  64. };
  65. static const struct udevice_id altera_timer_ids[] = {
  66. { .compatible = "altr,timer-1.0" },
  67. {}
  68. };
  69. U_BOOT_DRIVER(altera_timer) = {
  70. .name = "altera_timer",
  71. .id = UCLASS_TIMER,
  72. .of_match = altera_timer_ids,
  73. .of_to_plat = altera_timer_of_to_plat,
  74. .plat_auto = sizeof(struct altera_timer_plat),
  75. .probe = altera_timer_probe,
  76. .ops = &altera_timer_ops,
  77. };