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adjust DDR frequency from 800MHz to 720MHz, ArkMicro 20221122

lixh 2 years ago
parent
commit
8aeb6bfb8c

BIN
bootstrap/ark1668e_devb/ARKSDLDR.bin


+ 12 - 20
u-boot/arch/arm/mach-arkmicro/ddr_ark1668e.c

@@ -110,10 +110,6 @@
 #define DDR_CFG_0   	   *((volatile unsigned int *)(AHB_SYS_BASE + 0x210))
 #define DDR_CFG_1   	   *((volatile unsigned int *)(AHB_SYS_BASE + 0x214))
 
-
-#define  DDR_RATE   1600
-
-
 #define DDR3_1600
 
 #ifdef  DDR3_1600 
@@ -265,26 +261,22 @@ int DDRTraining(void)
 //#if 1
 unsigned int ddr3_sdramc_init(void)
 {
-	unsigned i;
 	int dll_frange=0;
 //softa
 	SYS_SOFT_RST_N_B = 0xfffffffd;
 	udelay (1); //
-	if(DDR_RATE<400)    
-	dll_frange = 0;
-	else if(400<=DDR_RATE<600)
-	dll_frange = 1;
-	else if(600<=DDR_RATE<700)
-	dll_frange = 2;
-	else if(700<=DDR_RATE<800)
-	dll_frange = 3;
-	else if(800<=DDR_RATE<900)  
-	dll_frange = 4;
-	else if(900<=DDR_RATE<1000)
-	dll_frange = 5;
-	else if(1000<=DDR_RATE<1200) 
-	dll_frange = 6;
-	else if(1200<=DDR_RATE)  
+
+	/*
+	dll_frange	ddr data rate(freq*2)
+		0	:	[0-400)
+		1	:	[400-600)
+		2	:	[600-700)
+		3	:	[700-800)
+		4	:	[800-900)
+		5	:	[900-1000)
+		6	:	[1000-1200)
+		7	:	[1200-1600)
+	*/
 	dll_frange = 7;
 	DDR_CFG_0 = 0x06060860|(dll_frange<<28);
 //apb_sys, DDR_CFG_1

+ 1 - 1
u-boot/arch/arm/mach-arkmicro/spl_ark1668e.c

@@ -12,7 +12,7 @@
 #define AXIPLL_CLK	720
 #define AHBPLL_CLK	336
 #define APBPLL_CLK	552
-#define DDRPLL_CLK  400
+#define DDRPLL_CLK  360
 #define MACPLL_CLK	1000
 #define AUDPLL_CLK	720