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@@ -21,32 +21,7 @@
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#define DMAC_MAX_CHANNELS 8
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#define DMAC_MAX_MASTERS 2
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#define DMAC_MAX_BLK_SIZE 0x200000
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-#define DMAX_MAX_BLK_MASK (0x1fffff)
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-#define DMAC_MAX_NR_REQUESTS 32
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-
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-/* Bitfields in LLP */
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-#define DWC_LLP_LMS(x) ((x) & 1) /* list master select */
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-#define DWC_LLP_LOC(x) ((x) & ~0x3f) /* next lli */
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-
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-
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-/**
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- * struct dw_axi_dma_slave - Controller-specific information about a slave
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- *
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- * @dma_dev: required DMA master device
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- * @src_id: src request line
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- * @dst_id: dst request line
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- * @m_master: memory master for transfers on allocated channel
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- * @p_master: peripheral master for transfers on allocated channel
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- * @hs_polarity:set active low polarity of handshake interface
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- */
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-struct dw_axi_dma_slave {
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- struct device *dma_dev;
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- u8 src_id;
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- u8 dst_id;
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- u8 m_master;
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- u8 p_master;
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- bool hs_polarity;
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-};
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+#define DMAX_MAX_BLK_MASK 0x1fffff
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struct dw_axi_dma_hcfg {
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u32 nr_channels;
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@@ -63,27 +38,24 @@ struct axi_dma_chan {
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struct axi_dma_chip *chip;
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void __iomem *chan_regs;
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u8 id;
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+ u8 hw_handshake_num;
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atomic_t descs_allocated;
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+ struct dma_pool *desc_pool;
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struct virt_dma_chan vc;
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+ struct axi_dma_desc *desc;
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+ struct dma_slave_config config;
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+ enum dma_transfer_direction direction;
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+ bool cyclic;
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/* these other elements are all protected by vc.lock */
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bool is_paused;
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-
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- enum dma_transfer_direction direction;
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-
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- /* custom slave configuration */
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- struct dw_axi_dma_slave dws;
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-
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- /* configuration passed via .device_config */
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- struct dma_slave_config dma_sconfig;
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- int cyclic;
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};
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struct dw_axi_dma {
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struct dma_device dma;
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struct dw_axi_dma_hcfg *hdata;
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- struct dma_pool *desc_pool;
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+ struct device_dma_parameters dma_parms;
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/* channels */
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struct axi_dma_chan *chan;
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@@ -115,13 +87,20 @@ struct __packed axi_dma_lli {
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__le32 reserved_hi;
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};
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+struct axi_dma_hw_desc {
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+ struct axi_dma_lli *lli;
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+ dma_addr_t llp;
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+ u32 len;
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+};
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+
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struct axi_dma_desc {
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- struct axi_dma_lli lli;
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+ struct axi_dma_hw_desc *hw_desc;
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+
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struct virt_dma_desc vd;
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struct axi_dma_chan *chan;
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- struct list_head xfer_list;
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- size_t len;
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- size_t total_len;
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+ u32 completed_blocks;
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+ u32 length;
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+ u32 period_len;
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};
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static inline struct device *dchan2dev(struct dma_chan *dchan)
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@@ -193,6 +172,7 @@ static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
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#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
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#define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */
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+#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
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/* DMAC_CFG */
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#define DMAC_EN_POS 0
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@@ -208,7 +188,6 @@ static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
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#define DMAC_CHAN_SUSP_WE_SHIFT 24
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/* CH_CTL_H */
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-#define CH_CTL_H_IOC_BLKTFR_EN BIT(26)
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#define CH_CTL_H_ARLEN_EN BIT(6)
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#define CH_CTL_H_ARLEN_POS 7
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#define CH_CTL_H_AWLEN_EN BIT(15)
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@@ -236,8 +215,6 @@ enum {
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#define CH_CTL_L_DST_MSIZE_POS 18
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#define CH_CTL_L_SRC_MSIZE_POS 14
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-#define DWC_CTLL_DST_MSIZE(n) ((n)<<CH_CTL_L_DST_MSIZE_POS) /* burst, #elements */
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-#define DWC_CTLL_SRC_MSIZE(n) ((n)<<CH_CTL_L_SRC_MSIZE_POS)
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enum {
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DWAXIDMAC_BURST_TRANS_LEN_1 = 0,
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@@ -254,8 +231,6 @@ enum {
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#define CH_CTL_L_DST_WIDTH_POS 11
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#define CH_CTL_L_SRC_WIDTH_POS 8
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-#define DWC_CTLL_DST_WIDTH(n) ((n)<<CH_CTL_L_DST_WIDTH_POS) /* bytes per element */
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-#define DWC_CTLL_SRC_WIDTH(n) ((n)<<CH_CTL_L_SRC_WIDTH_POS)
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#define CH_CTL_L_DST_INC_POS 6
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#define CH_CTL_L_SRC_INC_POS 4
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@@ -263,15 +238,9 @@ enum {
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DWAXIDMAC_CH_CTL_L_INC = 0,
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DWAXIDMAC_CH_CTL_L_NOINC
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};
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-#define DWC_CTLL_DST_INC (DWAXIDMAC_CH_CTL_L_INC<<CH_CTL_L_DST_INC_POS) /* DAR update/not */
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-#define DWC_CTLL_DST_FIX (DWAXIDMAC_CH_CTL_L_NOINC<<CH_CTL_L_DST_INC_POS)
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-#define DWC_CTLL_SRC_INC (DWAXIDMAC_CH_CTL_L_INC<<CH_CTL_L_SRC_INC_POS) /* SAR update/not */
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-#define DWC_CTLL_SRC_FIX (DWAXIDMAC_CH_CTL_L_NOINC<<CH_CTL_L_SRC_INC_POS)
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#define CH_CTL_L_DST_MAST BIT(2)
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#define CH_CTL_L_SRC_MAST BIT(0)
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-#define DWC_CTLL_DMS(n) ((n)<<2) /* dst master select */
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-#define DWC_CTLL_SMS(n) ((n)<<0) /* src master select */
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/* CH_CFG_H */
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#define CH_CFG_H_PRIORITY_POS 17
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@@ -293,7 +262,6 @@ enum {
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DWAXIDMAC_TT_FC_MEM_TO_PER_DST,
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DWAXIDMAC_TT_FC_PER_TO_PER_DST
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};
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-#define DWC_CFGH_FC(n) ((n) << CH_CFG_H_TT_FC_POS)
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/* CH_CFG_L */
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#define CH_CFG_L_DST_PER_POS 11
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