修复小概率不能正常录放音的问题

linux/arch/arm/boot/dts/ark1668e.dtsi

@@ -383,7 +383,7 @@
 				index-value = <2>;
 				div-offset = <11>;
 				div-mask = <0xf>;
-				div-value = <2>;
+				div-value = <3>;
 				div-mode = <ARK_CLK_DIVMODE_NOZERO>;
 				enable-reg = <0x44 0x4c 0x50>;
 				enable-offset = <19 8 23>;
@@ -399,7 +399,7 @@
 				index-value = <1>;
 				div-offset = <24>;
 				div-mask = <0xf>;
-				div-value = <3>;
+				div-value = <2>;
 				div-mode = <ARK_CLK_DIVMODE_NOZERO>;
 				//enable-reg = <0x44 0x4c 0x50 0x50>;
 				//enable-offset = <21 15 25 14>;
@@ -504,7 +504,7 @@
 			compatible = "snps,axi-dma-1.01a";
 			reg = <0xe0000000 0x1000>;
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&axipll>, <&axipll>;
+			clocks = <&ahbpll>, <&ahbpll>;
 			clock-names = "core-clk", "cfgr-clk";
 			#dma-cells = <3>;
 

linux/drivers/dma/ark-axi-dma.c

@@ -969,7 +969,8 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
 
 	if (!vd) {
 		spin_unlock_irqrestore(&chan->vc.lock, flags);
-		return;
+		return;	
+
 	}
 
 	if (chan->cyclic) {

u-boot/arch/arm/mach-arkmicro/spl_ark1668e.c

@@ -9,7 +9,7 @@
 
 #define CPUPLL_CLK  800
 #define LCDPLL_CLK	480
-#define AXIPLL_CLK	480	//720
+#define AXIPLL_CLK	480
 #define AHBPLL_CLK	336
 #define APBPLL_CLK	552
 #define DDRPLL_CLK  400