降低AUDPLL时钟频率，避免设置8K采样率时造成的寄存器值溢出

u-boot/arch/arm/mach-arkmicro/spl_ark1668e.c

@@ -12,7 +12,7 @@
 #define APBPLL_CLK	480
 #define DDRPLL_CLK  360
 #define MACPLL_CLK	1000
-#define AUDPLL_CLK	720
+#define AUDPLL_CLK	480
 enum sscg_clk_id {
 	SSCG_CPU,
 	SSCG_LCD,