// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/ark-clk.h>

#define DDR512

/ {
	model = "ARM Arkmicro ark1668e SoC";
	compatible = "arkmicro,ark1668e";

	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		hsserial0 = &hsuart0;
		hsserial1 = &hsuart1;
		usb0 = &usb0;
		usb1 = &usb1;
	};

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk loglevel=8 clk_ignore_unused";
		stdout-path = "serial0:115200n8";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "arkmicro,arke-smp";

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clock-frequency = <800000000>;
			next-level-cache = <&L2_CA7>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
			clock-frequency = <800000000>;
			next-level-cache = <&L2_CA7>;
		};

		L2_CA7: cache-controller-0 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
		};
	};

	memory {
#ifdef DDR512
		reg = <0x40000000 0x1e000000>;
#else
		reg = <0x40000000 0xe000000>;
#endif
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
#ifdef DDR512
			size = <0x8000000>;
#else
			size = <0x4000000>;
#endif
			linux,cma-default;
		};
	};

	iram {
		compatible = "arkmicro,arke-iram";
		reg = <0x300000 0x8000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		arm,cpu-registers-not-fw-configured;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	sregs@e4900000 {
		compatible = "arkmicro,ark-sregs";
		reg = <0xe4900000 0x1000>;

		clocks {
			#address-cells = <1>;
			#size-cells = <0>;

			xtal32k: xtal32k@32K {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <32768>;
			};

			xtal24mhz: xtal24mhz@24M {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <24000000>;
			};

			xtal25mhz: xtal25mhz@25M {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <25000000>;
			};

			clk240mhz: clk240mhz@240M {
				#clock-cells = <0>;
				compatible = "fixed-factor-clock";
				clock-div = <1>;
				clock-mult = <10>;
				clocks = <&xtal24mhz>;
			};

			clk12mhz: clk12mhz@12M {
				#clock-cells = <0>;
				compatible = "fixed-factor-clock";
				clock-div = <2>;
				clock-mult = <1>;
				clocks = <&xtal24mhz>;
			};

			clk6mhz: clk6mhz@6M {
				#clock-cells = <0>;
				compatible = "fixed-factor-clock";
				clock-div = <4>;
				clock-mult = <1>;
				clocks = <&xtal24mhz>;
			};

			cpupll: cpupll {
				#clock-cells = <0>;
				compatible = "arkmiro,arke-clk-sscg";
				clocks = <&xtal24mhz>;
				reg = <0x280>;
				reg2 = <0x284>;
			};

			lcdpll: lcdpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arke-clk-sscg";
				clocks = <&xtal24mhz>;
				reg = <0x28c>;
				reg2 = <0x290>;
			};

			macpll: macpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arke-clk-sscg";
				clocks = <&xtal24mhz>;
				reg = <0x2b4>;
				reg2 = <0x2b8>;
				clk-can-change;
			};

			axipll: axipll {
				#clock-cells = <0>;
				compatible = "arkmiro,arke-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x298>;
			};

			ahbpll: ahbpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arke-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x29c>;
			};

			apbpll: apbpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arke-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x2a0>;
			};

			ddrpll: ddrpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arke-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x2a8>;
			};

			audpll: audpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arke-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x2a4>;
			};

			tvpll: tvpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arke-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x2ac>;
			};

			apbclk: apbclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&apbpll>, <&axipll>, <&macpll>, <&xtal24mhz>;
				reg = <0x40>;
				index-offset = <0>;
				index-mask = <0xf>;
				div-offset = <4>;
				div-mask = <0xf>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;	
			};

			apbclk1: apbclk1 {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&ahbpll>, <&axipll>, <&apbpll>, <&xtal24mhz>;
				reg = <0x22c>;
				index-offset = <4>;
				index-mask = <0x7>;
				div-offset = <0>;
				div-mask = <0x7>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;
			};

			hsuart0clk: hsuart0clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal24mhz>, <&apbclk1>;
				reg = <0x6c>;
				index-offset = <12>;
				index-mask = <0x1>;
				index-value = <0>;
				div-offset = <8>;
				div-mask = <0xf>;
				div-value = <0>;
				div-mode = <ARK_CLK_DIVMODE_NOZERO>;
				enable-reg = <0x48 0x50>;
				enable-offset = <9 9>;
			};

			hsuart1clk: hsuart1clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal24mhz>, <&apbclk1>;
				reg = <0x6c>;
				index-offset = <17>;
				index-mask = <0x1>;
				index-value = <0>;
				div-offset = <13>;
				div-mask = <0xf>;
				div-value = <0>;
				div-mode = <ARK_CLK_DIVMODE_NOZERO>;
				enable-reg = <0x48 0x50>;
				enable-offset = <10 10>;
			};

			pwmclk: pwmclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal24mhz>, <&apbpll>;
				reg = <0x60>;
				index-offset = <8>;
				index-mask = <0x1>;
				index-value = <0>;
				div-offset = <4>;
				div-mask = <0xf>;
				div-value = <1>;
				div-mode = <ARK_CLK_DIVMODE_NOZERO>;
				enable-reg = <0x48 0x50>;
				enable-offset = <13 27>;			
			};

			rtc_clk: rtc-clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal32k>;
				reg = <0x48>;
				enable-reg = <0x48>;
				enable-offset = <6>;
			};

			ssi_clk: ssi-clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&ahbpll>, <&axipll>, <&apbpll>, <&xtal24mhz>;
				reg = <0x60>;
				index-offset = <20>;
				index-mask = <0xf>;
				index-value = <1>;
				div-offset = <16>;
				div-mask = <0xf>;
				div-value = <6>;
				div-mode = <ARK_CLK_DIVMODE_PONEDOUBLE>;
				enable-reg = <0x48 0x50>;
				enable-offset = <4 13>;
			};

			spi_clk: spi-clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&ahbpll>, <&axipll>, <&apbpll>, <&xtal24mhz>;
				reg = <0x228>;
				index-offset = <4>;
				index-mask = <0xf>;
				index-value = <1>;
				div-offset = <0>;
				div-mask = <0xf>;
				div-value = <6>;
				div-mode = <ARK_CLK_DIVMODE_PONEDOUBLE>;
				enable-reg = <0x48>;
				enable-offset = <24>;
			};

			mmc0clk: mmc0clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&apbpll>, <&axipll>, <&ahbpll>, <&xtal24mhz>;
				reg = <0x58>;
				index-offset = <8>;
				index-mask = <0xf>;
				index-value = <0>;
				div-offset = <0>;
				div-mask = <0x1f>;
				div-value = <10>;
				div-mode = <ARK_CLK_DIVMODE_PONEDOUBLE>;
				enable-reg = <0x58 0x58>;
				enable-offset = <5 7>;
			};

			mmc1clk: mmc1clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&apbpll>, <&axipll>, <&ahbpll>, <&xtal24mhz>;
				reg = <0x5c>;
				index-offset = <8>;
				index-mask = <0xf>;
				index-value = <0>;
				div-offset = <0>;
				div-mask = <0x1f>;
				div-value = <10>;
				div-mode = <ARK_CLK_DIVMODE_PONEDOUBLE>;
				enable-reg = <0x5c 0x5c>;
				enable-offset = <5 7>;
			};

			mmc2clk: mmc2clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&apbpll>, <&axipll>, <&ahbpll>, <&xtal24mhz>;
				reg = <0x7c>;
				index-offset = <8>;
				index-mask = <0xf>;
				index-value = <0>;
				div-offset = <0>;
				div-mask = <0x1f>;
				div-value = <10>;
				div-mode = <ARK_CLK_DIVMODE_PONEDOUBLE>;
				enable-reg = <0x7c 0x7c>;
				enable-offset = <5 7>;
			};

			lcdclkdiv: lcdclkdiv {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&lcdpll>, <&axipll>, <&tvpll>, <&xtal24mhz>;
				reg = <0x54>;
				index-offset = <7>;
				index-mask = <0xf>;
				index-value = <0>;
				div-offset = <4>;
				div-mask = <0x7>;
				div-value = <1>;
			};

			lcdclk: lcdclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&lcdclkdiv>;
				reg = <0x54>;
				div-offset = <19>;
				div-mask = <0xf>;
				div-value = <4>;
				clk-can-change;
				enable-reg = <0x44 0x4c 0x50>;
				enable-offset = <8 1 4>;
			};

			mfcclk: mfcclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&ahbpll>, <&axipll>, <&apbpll>, <&xtal24mhz>;
				reg = <0x64>;
				index-offset = <16>;
				index-mask = <0x7>;
				div-offset = <19>;
				div-mask = <0xf>;
			};

			gpuclk: gpuclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&ahbpll>, <&axipll>, <&apbpll>, <&xtal24mhz>;
				reg = <0x17c>;
				index-offset = <8>;
				index-mask = <0x7>;
				index-value = <2>;
				div-offset = <11>;
				div-mask = <0xf>;
				div-value = <3>;
				div-mode = <ARK_CLK_DIVMODE_NOZERO>;
				enable-reg = <0x44 0x4c 0x50>;
				enable-offset = <19 8 23>;
			};			

			scalclk: scalclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&lcdpll>, <&axipll>, <&tvpll>, <&xtal24mhz>;
				reg = <0x228>;
				index-offset = <28>;
				index-mask = <0x7>;
				index-value = <1>;
				div-offset = <24>;
				div-mask = <0xf>;
				div-value = <2>;
				div-mode = <ARK_CLK_DIVMODE_NOZERO>;
				//enable-reg = <0x44 0x4c 0x50 0x50>;
				//enable-offset = <21 15 25 14>;
			};

			mac_txclk: mac_txclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&cpupll>, <&lcdpll>, <&macpll>, <&xtal24mhz>;
				reg = <0x234>;
				index-offset = <29>;
				index-mask = <0x7>;
				index-value = <2>;
				div-offset = <24>;
				div-mask = <0xf>;
				div-value = <8>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;
				enable-reg = <0x234>;
				enable-offset = <28>;
				clk-can-change;
			};

			mac_ptpclk: mac_ptpclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&ahbpll>, <&axipll>, <&apbpll>, <&xtal24mhz>;
				reg = <0x230>;
				index-offset = <8>;
				index-mask = <0x7>;
				index-value = <3>;
				div-offset = <12>;
				div-mask = <0xf>;
				div-value = <1>;
				div-mode = <ARK_CLK_DIVMODE_NOZERO>;
			};

			i2s_adc_clk: i2s_adc_clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal24mhz>, <&audpll>;
				reg = <0x6c>;
				index-offset = <0>;
				index-mask = <0x1>;
				index-value = <1>;
			};

			i2s_dac_clk: i2s_dac_clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal24mhz>, <&audpll>;
				reg = <0x6c>;
				index-offset = <2>;
				index-mask = <0x1>;
				index-value = <1>;
			};

			i2s2_dac_clk: i2s2_dac_clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal24mhz>, <&audpll>;
				reg = <0x6c>;
				index-offset = <4>;
				index-mask = <0x1>;
				index-value = <1>;
			};

			can_clk: can_clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&apbclk>;
				reg = <0>;
			};

			gpio_debnc_clk: gpio_debnc_clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&rtc_clk>, <&xtal24mhz>;
				reg = <0x60>;
				index-offset = <31>;
				index-mask = <0x1>;
				index-value = <1>;
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gic: interrupt-controller@e0b01000 {
			compatible = "arm,cortex-a7-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xe0b01000 0x1000>,
			      <0xe0b02000 0x2000>,
			      <0xe0b04000 0x2000>,
			      <0xe0b06000 0x2000>;
			//interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		pinctrl0: pinctrl@e4900000 {
			compatible = "arkmicro,arke-pinctrl";
			reg = <0xe4900000 0x1000>;
			pad-reg-offset = <0x1c0>;
			npins = <192>;
			gpio-mux-pins = <170>;
		};

		dmac: dmac@e0000000 {
			compatible = "snps,axi-dma-1.01a";
			reg = <0xe0000000 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ahbpll>, <&ahbpll>;
			clock-names = "core-clk", "cfgr-clk";
			#dma-cells = <3>;

			dma-channels = <8>;
			snps,dma-masters = <2>;
			snps,data-width = <3>;
			snps,block-size = <65536 65536 65536 65536
								65536 65536 65536 65536>;
			snps,priority = <0 1 2 3 4 5 6 7>;
			snps,axi-max-burst-len = <16>;
		};

		i2s_adc: i2s-adc@e4000000 {
			compatible = "arkmicro,ark1668e-i2s";
			reg = <0xe4000000 0x1000>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			nco-reg = <0xe4900174>;
			dmas = <&dmac 0 1 0>, <&dmac 1 0 1>;
			dma-names = "rx", "tx";
			clocks = <&i2s_adc_clk>;
			#sound-dai-cells = <0>;
		};

		i2s_dac: i2s-dac@e4200000 {
			compatible = "arkmicro,ark1668e-i2s";
			reg = <0xe4200000 0x1000>;
			//full-duplex-mode;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			nco-reg = <0xe490019c>;
			dmas = <&dmac 25 1 0>, <&dmac 26 0 1>;
			dma-names = "rx", "tx";
			clocks = <&i2s_dac_clk>;
			#sound-dai-cells = <0>;
		};

		i2s2_dac: i2s2-dac@e4800000 {
			compatible = "arkmicro,ark1668e-i2s";
			reg = <0xe4800000 0x1000>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			nco-reg = <0xe4900178>;
			dmas = <&dmac 23 1 0>, <&dmac 24 0 1>;
			dma-names = "rx", "tx";
			clocks = <&i2s2_dac_clk>;
			#sound-dai-cells = <0>;
		};

		ark_codec: ark-adac@e4900000 {
			compatible = "arkmicro,ark-audio-codec";
			reg = <0xe4900000 0x1000>;
			#sound-dai-cells = <0>;
		};

		uart0: uart@e8200000 {
			compatible = "arkmicro,ark-uart";
			reg = <0xe8200000 0x1000>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			current-speed = <115200>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&xtal24mhz>;
			//dmas = <&dmac 6 1 0>, <&dmac 7 0 1>;
			//dma-names = "rx", "tx";
		};

		uart1: uart@e8300000 {
			compatible = "arkmicro,ark-uart";
			reg = <0xe8300000 0x1000>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			current-speed = <115200>;
			clocks = <&xtal24mhz>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			//dmas = <&dmac 12 1 0>, <&dmac 13 0 1>;
			//dma-names = "rx", "tx";
		};

		uart2: uart@e8400000 {
			compatible = "arkmicro,ark-uart";
			reg = <0xe8400000 0x1000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			current-speed = <115200>;
			clocks = <&xtal24mhz>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			//dmas = <&dmac 19 1 0>, <&dmac 20 0 1>;//19 , 20
			//dma-names = "rx", "tx";
		};

		uart3: uart@e8500000 {
			compatible = "arkmicro,ark-uart";
			reg = <0xe8500000 0x1000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			current-speed = <115200>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&xtal24mhz>;
			//dmas = <&dmac 21 1 0>, <&dmac 22 0 1>;//21 , 22
			//dma-names = "rx", "tx";
		};

		hsuart0: hsuart@e8000000 {
			compatible = "arkmicro,ark-hsuart";
			reg = <0xe8000000 0x4000>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsuart0clk>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_hsuart0>;
			dmas = <&dmac 14 1 0>;//, <&dmac 15 0 1>;//14 , 15
			dma-names = "rx";//, "tx";
		};

		hsuart1: hsuart@e8100000 {
			compatible = "arkmicro,ark-hsuart";
			reg = <0xe8100000 0x4000>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsuart1clk>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_hsuart1>;
			dmas = <&dmac 16 1 0>, <&dmac 17 0 1>;//16 , 17
			dma-names = "rx", "tx";
		};

		can0: can0@e4400000 {
			compatible = "nxp,sja1000";
			reg = <0xe4400000 0x1000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_can0>;
			clocks = <&apbclk>;
			//nxp,external-clock-frequency = <120000000>;
			status = "disabled";
		};

		can1: can1@e4a00000 {
			compatible = "nxp,sja1000";
			reg = <0xe4a00000 0x1000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_can1>;
			clocks = <&apbclk>;
			//nxp,external-clock-frequency = <120000000>;
			status = "disabled";
		};

		timer0: timer@e8600000 {
			compatible = "snps,dw-apb-timer-osc";
			reg = <0xe8600000 0x14>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&xtal24mhz>, <&apbclk>;
			clock-names = "timer", "pclk";
		};

		timer1: timer@e8600014 {
			compatible = "snps,dw-apb-timer-osc";
			reg = <0xe8600014 0x14>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&xtal24mhz>, <&apbclk>;
			clock-names = "timer", "pclk";
		};

		watchdog: watchdog@e4b00000 {
			compatible = "arkmicro,ark-wdt";
			reg = <0xe4b00000 0x20>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apbclk>;
		};

		gpio0: gpio@e4600000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xe4600000 0x80>;

			gporta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				base = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 0 32>;
			};
		};

		gpio1: gpio@e4600080 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xe4600080 0x80>;

			gportb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				base = <32>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 32 32>;
			};
		};

		gpio2: gpio@e4600100 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xe4600100 0x80>;

			gportc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				base = <64>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 64 32>;
			};
		};

		gpio3: gpio@e4600180 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xe4600180 0x80>;

			gportd: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				base = <96>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 96 32>;
			};
		};

		gpio4: gpio@e4600200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xe4600200 0x80>;

			gporte: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				base = <128>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 128 32>;
			};
		};

		gpio5: gpio@e4600280 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xe4600280 0x80>;

			gportf: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				base = <160>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 160 32>;
			};
		};

		pwm0: pwm@e4d00000 {
			compatible = "arkmicro,ark-pwm";
			reg = <0xe4d00000 0x100>;
			#pwm-cells = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_pwm0 &pinctrl_pwm1 &pinctrl_pwm2 &pinctrl_pwm3>;
			clocks = <&pwmclk>;
		};

        nfc: nand@ec000000 {
            compatible = "arkmicro,ark-nand";
            reg = <0xec000000 0x1000>;
            max-chips = <1>;
            interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
            nand-bus-width = <8>;
            nand-ecc-mode = "hw_syndrome";
            nand-on-flash-bbt;
        };

		rtc: rtc@e4c00000 {
			compatible = "arkmicro,ark-rtc";
			reg = <0xe4c00000 0x100>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rtc_clk>;
		};

		mmc0: mmc@ec400000 {
			compatible = "snps,dw-mshc";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xec400000 0x1000>;
            interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <64>;
			bus-width = <8>;
            cap-mmc-highspeed;
            disable-wp;
            non-removable;
			clocks = <&mmc0clk>;
			clock-names = "ciu";
		};

		mmc1: mmc@ec800000 {
			compatible = "snps,dw-mshc";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xec800000 0x1000>;
            interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <64>;
			bus-width = <4>;
			clocks = <&mmc1clk>;
			clock-names = "ciu";
		};

		mmc2: mmc@ecc00000 {
			compatible = "snps,dw-mshc";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xecc00000 0x1000>;
            interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <64>;
			bus-width = <4>;
			#supports-SDIO;
			#cap-sd-highspeed;
			#cap-sdio-irq;
			clocks = <&mmc2clk>;
			clock-names = "ciu";
		};

		i2c0: i2c@e4300000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "arkmicro,ark-i2c";
			reg = <0xe4300000 0x1000>;
			speed-mode = <0>; //0:standard 1:fast 2:high
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&xtal24mhz>;
			resets = <&rst 0x74 15>;
			reset-names = "i2c0";
		};

		ecspi: ecspi@e4f00000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "arkmicro,arke-ecspi";
			reg = <0xe4f00000 0x1000>;
			num-chipselect = <1>;
			chipselects = <161>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			//dmas = <&dmac 27 1 0>, <&dmac 28 0 1>;
			//dma-names = "rx", "tx";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_ecspi>;
			clocks = <&spi_clk>, <&spi_clk>;
			clock-names = "ipg", "per";
			status = "disabled";

			m25p80@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "w25q128";
				reg = <0>; /* Chip select 0 */
				spi-max-frequency = <3000000>;
				status = "disabled";
			};

			gd5f@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "gd5f";
				reg = <0>; /* Chip select 0 */
				spi-max-frequency = <3000000>;
				status = "disabled";
			};
		};

		dwssi: dwssi@e4100000 {
			compatible = "arkmicro,ark-dw-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xe4100000 0x100>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
			num-cs = <1>;
			cs-gpios = <&gportd 5 0>;

			//tx-dma-channel = <&pdma 16>;
			//rx-dma-channel = <&pdma 17>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_dwssi>;
			clocks = <&ssi_clk>;
			status = "disabled";

			m25p80@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "w25q256";
				reg = <0>; /* Chip select 0 */
				spi-max-frequency = <3000000>;
				//spi-tx-bus-width = <1>;
				//spi-rx-bus-width = <4>;
				status = "disabled";
			};

			gd5f@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "gd5f";
				reg = <0>; /* Chip select 0 */
				spi-max-frequency = <3000000>;
				status = "disabled";
			};
		};

		vdec0: vdec@e0900000 {
			compatible = "on2,ark-vdec";
			reg = <0xe0900000 0x1000
#ifdef DDR512
					0x5e000000 0x500000>;//max space 10Mbyte
#else
					0x4e000000 0x500000>;//max space 10Mbyte
#endif
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mfcclk>;
			clock-names = "vdec_clk";
			//status = "disabled";
		};

		ethernet: ethernet@e0300000 {
			compatible = "arkmicro,ark1668e-eqos", "snps,dwc-qos-ethernet-4.10";
			reg = <0xe0300000 0x4000>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			snps,write-requests = <2>;
			snps,read-requests = <16>;
			snps,txpbl = <8>;
			snps,rxpbl = <2>;
			clocks = <&macpll>, <&mac_txclk>, <&mac_txclk>, <&apbclk>;
			clock-names = "tx_src", "tx", "phy_ref_clk", "apb_pclk";
			status = "disabled";
		};

		gpu: gpu@e9000000 {
			compatible = "arm,mali-400", "arm,mali-utgard";
			reg = <0xe9000000 0x30000
#ifdef DDR512
					0x5f000000 0x1000000>;
#else
					0x4f000000 0x1000000>;
#endif
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
			//pmu_domain_config = <0x1 0x4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2 0x0 0x0>;
			//pmu_switch_delay = <0xff>;
			clocks = <&gpuclk>, <&gpuclk>;
			clock-names = "mali_parent", "mali";
			//status = "disabled";
		};

		lcdc: lcd@e0500000 {
			compatible = "arkmicro,ark1668e-lcdc";
			reg = <0xe0500000 0x1000
#ifdef DDR512
					0x5f000000 0x1000000>;
#else
					0x4f000000 0x1000000>;
#endif
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&lcdclk>;
			clock-names = "lcdc_clk";
		};


		usb0_phy: usb0-phy {
            compatible = "usb-nop-xceiv";
            #phy-cells = <0>;
            status = "disabled";
        };

        usb0: usb@e0100000{
            compatible = "arkmicro,ark-musb";
            status = "disabled";
            reg = <0xE0100000 0x1000    /* usb0 base address */
                    0xE4900000 0x1000>; /* ahb sys base address */
            reg-names = "system", "control";
			/* <usb0 int>, <usb0_dma_int> */
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "mc", "dma";
            dr_mode = "otg";
            multipoint = <1>;
            num-eps = <6>;
            ram-bits = <12>;
            //power = <500>;
            phys = <&usb0_phy>;
            gpio-id = <0xffffffff>;
            gpio-pwr = <0xffffffff>;
			usb-id-reg = <0x204>;
            usb-id-offset = <0>;
		    sys-softrest-regoffset = <0x74>;
		    usb-softrest-bitoffset = <5>;
			usbphy-softrest-bitoffset = <6>;
        };
        
        usb1_phy: usb1-phy {
            compatible = "usb-nop-xceiv";
            #phy-cells = <0>;
            status = "disabled";
        };
        
        usb1: usb@e0400000{
            compatible = "arkmicro,ark-musb";
            status = "disabled";
            reg = <0xE0400000 0x1000    /* usb0 base address */
                    0xE4900000 0x1000>; /* ahb sys base address */
            reg-names = "system", "control";
			/* <usb0 int>, <usb0_dma_int> */
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "mc", "dma";
            dr_mode = "otg";
            multipoint = <1>;
            num-eps = <6>;
            ram-bits = <12>;
            //power = <500>;
            phys = <&usb1_phy>;
            gpio-id = <0xffffffff>;
            gpio-pwr = <0xffffffff>;
			usb-id-reg = <0x204>;
            usb-id-offset = <2>;
		    sys-softrest-regoffset = <0x78>;
		    usb-softrest-bitoffset = <6>;
			usbphy-softrest-bitoffset = <7>;
        };

		axi_scale: axi-scale@e0600000 {
			compatible = "arkmicro,ark1668e-axi-scale";
			reg = <0xe0700000 0x1000
					0xe4900000 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scalclk>;
			softreset-reg = <0x74>;
			softreset-offset = <28>;
		};

		ituin: ituin@e0800000 {
			compatible = "arkmicro,ark1668e-vin";
			reg = <0xe0800000 0x1000
					0xe4900000 0x1000
					0xe0a00000 0x1000
					0xe0500000 0x1000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&pinctrl_hvsync &pinctrl_itu0>;
			pinctrl-1 = <&pinctrl_hvsync &pinctrl_itu1>;
			pinctrl-2 = <&pinctrl_hvsync &pinctrl_itu2>;
			pinctrl-names = "itu0", "itu1", "itu2";
			status = "disabled";
			port {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		rst: reset-controller {
			compatible = "arkmicro,ark-reset";
			#reset-cells = <2>;
			reg = <0xe4900000 0x1000>;
		};
	};
};