#ifndef ARK_NAND_H #define ARK_NAND_H /* NAND Flash Controller */ #define rNAND_CR ((CONFIG_SYS_NAND_BASE + 0x00)) #define rNAND_CLE_WR ((CONFIG_SYS_NAND_BASE + 0x04)) #define rNAND_ALE_WR ((CONFIG_SYS_NAND_BASE + 0x08)) #define rNAND_ID_RD ((CONFIG_SYS_NAND_BASE + 0x0c)) #define rNAND_STATUS_RD ((CONFIG_SYS_NAND_BASE + 0x10)) #define rNAND_DATA ((CONFIG_SYS_NAND_BASE + 0x14)) #define rNAND_TX_FIFO ((CONFIG_SYS_NAND_BASE + 0x18)) #define rNAND_RX_FIFO ((CONFIG_SYS_NAND_BASE + 0x1c)) #define rNAND_WRBLK_START ((CONFIG_SYS_NAND_BASE + 0x20)) #define rNAND_RDBLK_START ((CONFIG_SYS_NAND_BASE + 0x24)) #define rBCH_ENCODE_RESULT0_GROUP1 ((CONFIG_SYS_NAND_BASE + 0x28)) #define rBCH_ENCODE_RESULT1_GROUP1 ((CONFIG_SYS_NAND_BASE + 0x2c)) #define rBCH_ENCODE_RESULT2_GROUP1 ((CONFIG_SYS_NAND_BASE + 0x30)) #define rBCH_ENCODE_RESULT3_GROUP1 ((CONFIG_SYS_NAND_BASE + 0x34)) #define rBCH_ENCODE_RESULT4_GROUP1 ((CONFIG_SYS_NAND_BASE + 0x38)) #define rBCH_ENCODE_RESULT5_GROUP1 ((CONFIG_SYS_NAND_BASE + 0x3c)) #define rBCH_ENCODE_RESULT0_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x40)) #define rBCH_ENCODE_RESULT1_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x44)) #define rBCH_ENCODE_RESULT2_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x48)) #define rBCH_ENCODE_RESULT3_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x4c)) #define rBCH_ENCODE_RESULT4_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x50)) #define rBCH_ENCODE_RESULT5_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x54)) #define rBCH_ENCODE_RESULT0_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x58)) #define rBCH_ENCODE_RESULT1_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x5c)) #define rBCH_ENCODE_RESULT2_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x60)) #define rBCH_ENCODE_RESULT3_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x64)) #define rBCH_ENCODE_RESULT4_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x68)) #define rBCH_ENCODE_RESULT5_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x6c)) #define rBCH_ENCODE_RESULT0_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x70)) #define rBCH_ENCODE_RESULT1_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x74)) #define rBCH_ENCODE_RESULT2_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x78)) #define rBCH_ENCODE_RESULT3_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x7c)) #define rBCH_ENCODE_RESULT4_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x80)) #define rBCH_ENCODE_RESULT5_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x84)) #define rBCH_ENCODE_RESULT0_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x88)) #define rBCH_ENCODE_RESULT1_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x8c)) #define rBCH_ENCODE_RESULT2_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x90)) #define rBCH_ENCODE_RESULT3_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x94)) #define rBCH_ENCODE_RESULT4_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x98)) #define rBCH_ENCODE_RESULT5_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x9c)) #define rBCH_ENCODE_RESULT0_GROUP6 ((CONFIG_SYS_NAND_BASE + 0xa0)) #define rBCH_ENCODE_RESULT1_GROUP6 ((CONFIG_SYS_NAND_BASE + 0xa4)) #define rBCH_ENCODE_RESULT2_GROUP6 ((CONFIG_SYS_NAND_BASE + 0xa8)) #define rBCH_ENCODE_RESULT3_GROUP6 ((CONFIG_SYS_NAND_BASE + 0xac)) #define rBCH_ENCODE_RESULT4_GROUP6 ((CONFIG_SYS_NAND_BASE + 0xb0)) #define rBCH_ENCODE_RESULT5_GROUP6 ((CONFIG_SYS_NAND_BASE + 0xb4)) #define rBCH_ENCODE_RESULT0_GROUP7 ((CONFIG_SYS_NAND_BASE + 0xb8)) #define rBCH_ENCODE_RESULT1_GROUP7 ((CONFIG_SYS_NAND_BASE + 0xbc)) #define rBCH_ENCODE_RESULT2_GROUP7 ((CONFIG_SYS_NAND_BASE + 0xc0)) #define rBCH_ENCODE_RESULT3_GROUP7 ((CONFIG_SYS_NAND_BASE + 0xc4)) #define rBCH_ENCODE_RESULT4_GROUP7 ((CONFIG_SYS_NAND_BASE + 0xc8)) #define rBCH_ENCODE_RESULT5_GROUP7 ((CONFIG_SYS_NAND_BASE + 0xcc)) #define rBCH_ENCODE_RESULT0_GROUP8 ((CONFIG_SYS_NAND_BASE + 0xd0)) #define rBCH_ENCODE_RESULT1_GROUP8 ((CONFIG_SYS_NAND_BASE + 0xd4)) #define rBCH_ENCODE_RESULT2_GROUP8 ((CONFIG_SYS_NAND_BASE + 0xd8)) #define rBCH_ENCODE_RESULT3_GROUP8 ((CONFIG_SYS_NAND_BASE + 0xdc)) #define rBCH_ENCODE_RESULT4_GROUP8 ((CONFIG_SYS_NAND_BASE + 0xe0)) #define rBCH_ENCODE_RESULT5_GROUP8 ((CONFIG_SYS_NAND_BASE + 0xe4)) #define rBCH_DECODE_RESULT0_GROUP1 ((CONFIG_SYS_NAND_BASE + 0xe8)) #define rBCH_DECODE_RESULT1_GROUP1 ((CONFIG_SYS_NAND_BASE + 0xec)) #define rBCH_DECODE_RESULT2_GROUP1 ((CONFIG_SYS_NAND_BASE + 0xf0)) #define rBCH_DECODE_RESULT3_GROUP1 ((CONFIG_SYS_NAND_BASE + 0xf4)) #define rBCH_DECODE_RESULT4_GROUP1 ((CONFIG_SYS_NAND_BASE + 0xf8)) #define rBCH_DECODE_RESULT5_GROUP1 ((CONFIG_SYS_NAND_BASE + 0xfc)) #define rBCH_DECODE_RESULT6_GROUP1 ((CONFIG_SYS_NAND_BASE + 0x100)) #define rBCH_DECODE_RESULT0_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x104)) #define rBCH_DECODE_RESULT1_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x108)) #define rBCH_DECODE_RESULT2_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x10c)) #define rBCH_DECODE_RESULT3_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x110)) #define rBCH_DECODE_RESULT4_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x114)) #define rBCH_DECODE_RESULT5_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x118)) #define rBCH_DECODE_RESULT6_GROUP2 ((CONFIG_SYS_NAND_BASE + 0x11c)) #define rBCH_DECODE_RESULT0_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x120)) #define rBCH_DECODE_RESULT1_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x124)) #define rBCH_DECODE_RESULT2_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x128)) #define rBCH_DECODE_RESULT3_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x12c)) #define rBCH_DECODE_RESULT4_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x130)) #define rBCH_DECODE_RESULT5_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x134)) #define rBCH_DECODE_RESULT6_GROUP3 ((CONFIG_SYS_NAND_BASE + 0x138)) #define rBCH_DECODE_RESULT0_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x13c)) #define rBCH_DECODE_RESULT1_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x140)) #define rBCH_DECODE_RESULT2_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x144)) #define rBCH_DECODE_RESULT3_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x148)) #define rBCH_DECODE_RESULT4_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x14c)) #define rBCH_DECODE_RESULT5_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x150)) #define rBCH_DECODE_RESULT6_GROUP4 ((CONFIG_SYS_NAND_BASE + 0x154)) #define rBCH_DECODE_RESULT0_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x158)) #define rBCH_DECODE_RESULT1_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x15c)) #define rBCH_DECODE_RESULT2_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x160)) #define rBCH_DECODE_RESULT3_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x164)) #define rBCH_DECODE_RESULT4_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x168)) #define rBCH_DECODE_RESULT5_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x16c)) #define rBCH_DECODE_RESULT6_GROUP5 ((CONFIG_SYS_NAND_BASE + 0x170)) #define rBCH_DECODE_RESULT0_GROUP6 ((CONFIG_SYS_NAND_BASE + 0x174)) #define rBCH_DECODE_RESULT1_GROUP6 ((CONFIG_SYS_NAND_BASE + 0x178)) #define rBCH_DECODE_RESULT2_GROUP6 ((CONFIG_SYS_NAND_BASE + 0x17c)) #define rBCH_DECODE_RESULT3_GROUP6 ((CONFIG_SYS_NAND_BASE + 0x180)) #define rBCH_DECODE_RESULT3_GROUP6 ((CONFIG_SYS_NAND_BASE + 0x180)) #define rBCH_DECODE_RESULT4_GROUP6 ((CONFIG_SYS_NAND_BASE + 0x184)) #define rBCH_DECODE_RESULT5_GROUP6 ((CONFIG_SYS_NAND_BASE + 0x188)) #define rBCH_DECODE_RESULT6_GROUP6 ((CONFIG_SYS_NAND_BASE + 0x18c)) #define rBCH_DECODE_RESULT0_GROUP7 ((CONFIG_SYS_NAND_BASE + 0x190)) #define rBCH_DECODE_RESULT1_GROUP7 ((CONFIG_SYS_NAND_BASE + 0x194)) #define rBCH_DECODE_RESULT2_GROUP7 ((CONFIG_SYS_NAND_BASE + 0x198)) #define rBCH_DECODE_RESULT3_GROUP7 ((CONFIG_SYS_NAND_BASE + 0x19c)) #define rBCH_DECODE_RESULT4_GROUP7 ((CONFIG_SYS_NAND_BASE + 0x1a0)) #define rBCH_DECODE_RESULT5_GROUP7 ((CONFIG_SYS_NAND_BASE + 0x1a4)) #define rBCH_DECODE_RESULT6_GROUP7 ((CONFIG_SYS_NAND_BASE + 0x1a8)) #define rBCH_DECODE_RESULT0_GROUP8 ((CONFIG_SYS_NAND_BASE + 0x1ac)) #define rBCH_DECODE_RESULT1_GROUP8 ((CONFIG_SYS_NAND_BASE + 0x1b0)) #define rBCH_DECODE_RESULT2_GROUP8 ((CONFIG_SYS_NAND_BASE + 0x1b4)) #define rBCH_DECODE_RESULT3_GROUP8 ((CONFIG_SYS_NAND_BASE + 0x1b8)) #define rBCH_DECODE_RESULT4_GROUP8 ((CONFIG_SYS_NAND_BASE + 0x1bc)) #define rBCH_DECODE_RESULT5_GROUP8 ((CONFIG_SYS_NAND_BASE + 0x1c0)) #define rBCH_DECODE_RESULT6_GROUP8 ((CONFIG_SYS_NAND_BASE + 0x1c4)) #define rEX_BCH_ENCODE_SOURCE ((CONFIG_SYS_NAND_BASE + 0x1c8)) #define rEX_BCH_DECODE_SOURCE ((CONFIG_SYS_NAND_BASE + 0x1cc)) #define rEX_BCH_ENCODE_RESULT0 ((CONFIG_SYS_NAND_BASE + 0x1d0)) #define rEX_BCH_ENCODE_RESULT1 ((CONFIG_SYS_NAND_BASE + 0x1d4)) #define rEX_BCH_ENCODE_RESULT2 ((CONFIG_SYS_NAND_BASE + 0x1d8)) #define rEX_BCH_ENCODE_RESULT3 ((CONFIG_SYS_NAND_BASE + 0x1dc)) #define rEX_BCH_ENCODE_RESULT4 ((CONFIG_SYS_NAND_BASE + 0x1e0)) #define rEX_BCH_ENCODE_RESULT5 ((CONFIG_SYS_NAND_BASE + 0x1e4)) #define rEX_BCH_ENCODE_RESULT6 ((CONFIG_SYS_NAND_BASE + 0x1e8)) #define rEX_BCH_ENCODE_RESULT7 ((CONFIG_SYS_NAND_BASE + 0x1ec)) #define rEX_BCH_ENCODE_RESULT8 ((CONFIG_SYS_NAND_BASE + 0x1f0)) #define rEX_BCH_ENCODE_RESULT9 ((CONFIG_SYS_NAND_BASE + 0x1f4)) #define rEX_BCH_ENCODE_RESULT10 ((CONFIG_SYS_NAND_BASE + 0x1f8)) #define rEX_BCH_ENCODE_RESULT11 ((CONFIG_SYS_NAND_BASE + 0x1fc)) #define rEX_BCH_ENCODE_RESULT12 ((CONFIG_SYS_NAND_BASE + 0x200)) #define rEX_BCH_ENCODE_RESULT13 ((CONFIG_SYS_NAND_BASE + 0x204)) #define rEX_BCH_ENCODE_RESULT14 ((CONFIG_SYS_NAND_BASE + 0x208)) #define rEX_BCH_ENCODE_RESULT15 ((CONFIG_SYS_NAND_BASE + 0x20c)) #define rEX_BCH_ENCODE_RESULT16 ((CONFIG_SYS_NAND_BASE + 0x210)) #define rEX_BCH_ENCODE_RESULT17 ((CONFIG_SYS_NAND_BASE + 0x214)) #define rEX_BCH_ENCODE_RESULT18 ((CONFIG_SYS_NAND_BASE + 0x218)) #define rEX_BCH_ENCODE_RESULT19 ((CONFIG_SYS_NAND_BASE + 0x21c)) #define rEX_BCH_ENCODE_RESULT20 ((CONFIG_SYS_NAND_BASE + 0x220)) #define rEX_BCH_ENCODE_STATUS ((CONFIG_SYS_NAND_BASE + 0x274)) #define rEX_BCH_DECODE_STATUS ((CONFIG_SYS_NAND_BASE + 0x278)) #define rBCH_CR ((CONFIG_SYS_NAND_BASE + 0x27c)) #define rBCH_NAND_STATUS ((CONFIG_SYS_NAND_BASE + 0x280)) #define rBCH_DECODE_STATUS ((CONFIG_SYS_NAND_BASE + 0x284)) #define rBCH_INT ((CONFIG_SYS_NAND_BASE + 0x288)) #define rBCH_INT_MASK ((CONFIG_SYS_NAND_BASE + 0x28c)) #define rNAND_DMA_CTRL ((CONFIG_SYS_NAND_BASE + 0x290)) #define rNAND_GLOBAL_CTL ((CONFIG_SYS_NAND_BASE + 0x294)) #define rNAND_JUMP_CTL ((CONFIG_SYS_NAND_BASE + 0x298)) #define rEX_BCH_DECODE_RESULT0 ((CONFIG_SYS_NAND_BASE + 0x29c)) #define rEX_BCH_DECODE_RESULT1 ((CONFIG_SYS_NAND_BASE + 0x268)) #define rEX_BCH_DECODE_RESULT2 ((CONFIG_SYS_NAND_BASE + 0x26c)) #define rEX_BCH_DECODE_RESULT3 ((CONFIG_SYS_NAND_BASE + 0x270)) #define rEX_BCH_DECODE_RESULT4 ((CONFIG_SYS_NAND_BASE + 0x264)) #define rEX_BCH_DECODE_RESULT5 ((CONFIG_SYS_NAND_BASE + 0x268)) #define rEX_BCH_DECODE_RESULT6 ((CONFIG_SYS_NAND_BASE + 0x26c)) #define rEX_BCH_DECODE_RESULT7 ((CONFIG_SYS_NAND_BASE + 0x270)) #define rEX_BCH_DECODE_RESULT8 ((CONFIG_SYS_NAND_BASE + 0x264)) #define rEX_BCH_DECODE_RESULT9 ((CONFIG_SYS_NAND_BASE + 0x268)) #define rEX_BCH_DECODE_RESULT10 ((CONFIG_SYS_NAND_BASE + 0x26c)) #define rEX_BCH_DECODE_RESULT11 ((CONFIG_SYS_NAND_BASE + 0x270)) #define rEX_BCH_DECODE_RESULT12 ((CONFIG_SYS_NAND_BASE + 0x264)) #define rEX_BCH_DECODE_RESULT13 ((CONFIG_SYS_NAND_BASE + 0x268)) #define rEX_BCH_DECODE_RESULT14 ((CONFIG_SYS_NAND_BASE + 0x26c)) #define rEX_BCH_DECODE_RESULT15 ((CONFIG_SYS_NAND_BASE + 0x270)) #define rEX_BCH_DECODE_RESULT16 ((CONFIG_SYS_NAND_BASE + 0x264)) #define rEX_BCH_DECODE_RESULT17 ((CONFIG_SYS_NAND_BASE + 0x268)) #define rEX_BCH_DECODE_RESULT18 ((CONFIG_SYS_NAND_BASE + 0x26c)) #define rEX_BCH_DECODE_RESULT19 ((CONFIG_SYS_NAND_BASE + 0x270)) #define rEX_BCH_DECODE_RESULT20 ((CONFIG_SYS_NAND_BASE + 0x264)) #define rEX_BCH_DECODE_RESULT21 ((CONFIG_SYS_NAND_BASE + 0x268)) #define rEX_BCH_DECODE_RESULT22 ((CONFIG_SYS_NAND_BASE + 0x26c)) #define rEX_BCH_DECODE_RESULT23 ((CONFIG_SYS_NAND_BASE + 0x270)) #define ECCCODET0ADDR (CONFIG_SYS_NAND_BASE + 0x28) #define ECCCODET1ADDR (CONFIG_SYS_NAND_BASE + 0x2c) #define ECCCODET2ADDR (CONFIG_SYS_NAND_BASE + 0x30) #define ECCCODET3ADDR (CONFIG_SYS_NAND_BASE + 0x34) #define ECCCODET4ADDR (CONFIG_SYS_NAND_BASE + 0x38) #define ECCCODET5ADDR (CONFIG_SYS_NAND_BASE + 0x3c) //#define ECCRESULTADDR volatile UINT32*)((CONFIG_SYS_NAND_BASE + 0xe8) #define EX_BCH_ENCODE_RESULT_ADDR (CONFIG_SYS_NAND_BASE + 0x1d0) #define EX_BCH_DECODE_RESULT_ADDR (CONFIG_SYS_NAND_BASE + 0x29c) #define NAND_INT_GLOBAL (1<<3) #define NAND_INT_DECODE_ERR (1<<2) #define NAND_INT_DECODE_END (1<<1) #define NAND_INT_ENCODE_END (1<<0) //BCH_CR register fields defination #define BCH_CR_SECTOR_MODE (1<<8) #define BCH_CR_SECTOR_1K (1<<7) #define BCH_CR_ENCODER_RESET (1<<3) #define BCH_CR_DECODER_RESET (1<<2) #define BCH_CR_SOFT_ECC_ENABLE (1<<1) #define BCH_CR_BCH_ENABLE (1<<0) #define BCH_7BIT_SEL 0x0 #define BCH_13BIT_SEL 0x1 #define BCH_24BIT_SEL 0x2 #define BCH_30BIT_SEL 0x3 #define BCH_36BIT_SEL 0x4 #define BCH_CR_SECTOR_LENGTH (1<<7) #define BCH_BIT_SEL(x) (x<<4) #define NAND_PAGE_TYPE(x) (x<<25) #define NAND_SEL_CHIP(x) (x<<23) #define NAND_PRO_WRITE (1<<22) #define NAND_CE_ENABLE (1<<21) #define NAND_WR_SETPASS (0<<20) #define NAND_RD_TRP_NUM(x) (x<<16) #define NAND_RD_TREH_NUM(x) (x<<12) #define NAND_WR_HOLD_NUM(x) (x<<8) #define NAND_WR_WP_NUM(x) (x<<4) #define NAND_WR_SET_NUM(x) (x<<0) #endif /* ARK_NAND_H */