brcm,brcmstb.txt 7.2 KB

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  1. ARM Broadcom STB platforms Device Tree Bindings
  2. -----------------------------------------------
  3. Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
  4. SoC shall have the following DT organization:
  5. Required root node properties:
  6. - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
  7. example:
  8. / {
  9. #address-cells = <2>;
  10. #size-cells = <2>;
  11. model = "Broadcom STB (bcm7445)";
  12. compatible = "brcm,bcm7445", "brcm,brcmstb";
  13. Further, syscon nodes that map platform-specific registers used for general
  14. system control is required:
  15. - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
  16. - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
  17. "brcm,brcmstb-cpu-biu-ctrl",
  18. "syscon"
  19. - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
  20. cpu-biu-ctrl node
  21. -------------------
  22. SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
  23. specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
  24. complex to the different Memory Controller Ports (MCP), one per memory
  25. controller (MEMC). This BIU block offers a feature called Write Pairing which
  26. consists in collapsing two adjacent cache lines into a single (bursted) write
  27. transaction towards the memory controller (MEMC) to maximize write bandwidth.
  28. Required properties:
  29. - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"
  30. Optional properties:
  31. - brcm,write-pairing:
  32. Boolean property, which when present indicates that the chip
  33. supports write-pairing.
  34. example:
  35. rdb {
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. compatible = "simple-bus";
  39. ranges = <0 0x00 0xf0000000 0x1000000>;
  40. sun_top_ctrl: syscon@404000 {
  41. compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
  42. reg = <0x404000 0x51c>;
  43. };
  44. hif_cpubiuctrl: syscon@3e2400 {
  45. compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
  46. reg = <0x3e2400 0x5b4>;
  47. brcm,write-pairing;
  48. };
  49. hif_continuation: syscon@452000 {
  50. compatible = "brcm,bcm7445-hif-continuation", "syscon";
  51. reg = <0x452000 0x100>;
  52. };
  53. };
  54. Nodes that allow for support of SMP initialization and reboot are required:
  55. smpboot
  56. -------
  57. Required properties:
  58. - compatible
  59. The string "brcm,brcmstb-smpboot".
  60. - syscon-cpu
  61. A phandle / integer array property which lets the BSP know the location
  62. of certain CPU power-on registers.
  63. The layout of the property is as follows:
  64. o a phandle to the "hif_cpubiuctrl" syscon node
  65. o offset to the base CPU power zone register
  66. o offset to the base CPU reset register
  67. - syscon-cont
  68. A phandle pointing to the syscon node which describes the CPU boot
  69. continuation registers.
  70. o a phandle to the "hif_continuation" syscon node
  71. example:
  72. smpboot {
  73. compatible = "brcm,brcmstb-smpboot";
  74. syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
  75. syscon-cont = <&hif_continuation>;
  76. };
  77. reboot
  78. -------
  79. Required properties
  80. - compatible
  81. The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with
  82. the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm
  83. chips with the old SUN_TOP_CTRL interface.
  84. - syscon
  85. A phandle / integer array that points to the syscon node which describes
  86. the general system reset registers.
  87. o a phandle to "sun_top_ctrl"
  88. o offset to the "reset source enable" register
  89. o offset to the "software master reset" register
  90. example:
  91. reboot {
  92. compatible = "brcm,brcmstb-reboot";
  93. syscon = <&sun_top_ctrl 0x304 0x308>;
  94. };
  95. Power management
  96. ----------------
  97. For power management (particularly, S2/S3/S5 system suspend), the following SoC
  98. components are needed:
  99. = Always-On control block (AON CTRL)
  100. This hardware provides control registers for the "always-on" (even in low-power
  101. modes) hardware, such as the Power Management State Machine (PMSM).
  102. Required properties:
  103. - compatible : should contain "brcm,brcmstb-aon-ctrl"
  104. - reg : the register start and length for the AON CTRL block
  105. Example:
  106. aon-ctrl@410000 {
  107. compatible = "brcm,brcmstb-aon-ctrl";
  108. reg = <0x410000 0x400>;
  109. };
  110. = Memory controllers
  111. A Broadcom STB SoC typically has a number of independent memory controllers,
  112. each of which may have several associated hardware blocks, which are versioned
  113. independently (control registers, DDR PHYs, etc.). One might consider
  114. describing these controllers as a parent "memory controllers" block, which
  115. contains N sub-nodes (one for each controller in the system), each of which is
  116. associated with a number of hardware register resources (e.g., its PHY). See
  117. the example device tree snippet below.
  118. == MEMC (MEMory Controller)
  119. Represents a single memory controller instance.
  120. Required properties:
  121. - compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
  122. Should contain subnodes for any of the following relevant hardware resources:
  123. == DDR PHY control
  124. Control registers for this memory controller's DDR PHY.
  125. Required properties:
  126. - compatible : should contain one of these
  127. "brcm,brcmstb-ddr-phy-v71.1"
  128. "brcm,brcmstb-ddr-phy-v72.0"
  129. "brcm,brcmstb-ddr-phy-v225.1"
  130. "brcm,brcmstb-ddr-phy-v240.1"
  131. "brcm,brcmstb-ddr-phy-v240.2"
  132. - reg : the DDR PHY register range
  133. == DDR SHIMPHY
  134. Control registers for this memory controller's DDR SHIMPHY.
  135. Required properties:
  136. - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
  137. - reg : the DDR SHIMPHY register range
  138. == MEMC DDR control
  139. Sequencer DRAM parameters and control registers. Used for Self-Refresh
  140. Power-Down (SRPD), among other things.
  141. Required properties:
  142. - compatible : should contain one of these
  143. "brcm,brcmstb-memc-ddr-rev-b.2.1"
  144. "brcm,brcmstb-memc-ddr-rev-b.2.2"
  145. "brcm,brcmstb-memc-ddr-rev-b.2.3"
  146. "brcm,brcmstb-memc-ddr-rev-b.3.0"
  147. "brcm,brcmstb-memc-ddr-rev-b.3.1"
  148. "brcm,brcmstb-memc-ddr"
  149. - reg : the MEMC DDR register range
  150. Example:
  151. memory_controllers {
  152. ranges;
  153. compatible = "simple-bus";
  154. memc@0 {
  155. compatible = "brcm,brcmstb-memc", "simple-bus";
  156. ranges;
  157. ddr-phy@f1106000 {
  158. compatible = "brcm,brcmstb-ddr-phy-v240.1";
  159. reg = <0xf1106000 0x21c>;
  160. };
  161. shimphy@f1108000 {
  162. compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
  163. reg = <0xf1108000 0xe4>;
  164. };
  165. memc-ddr@f1102000 {
  166. reg = <0xf1102000 0x800>;
  167. compatible = "brcm,brcmstb-memc-ddr";
  168. };
  169. };
  170. memc@1 {
  171. compatible = "brcm,brcmstb-memc", "simple-bus";
  172. ranges;
  173. ddr-phy@f1186000 {
  174. compatible = "brcm,brcmstb-ddr-phy-v240.1";
  175. reg = <0xf1186000 0x21c>;
  176. };
  177. shimphy@f1188000 {
  178. compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
  179. reg = <0xf1188000 0xe4>;
  180. };
  181. memc-ddr@f1182000 {
  182. reg = <0xf1182000 0x800>;
  183. compatible = "brcm,brcmstb-memc-ddr";
  184. };
  185. };
  186. memc@2 {
  187. compatible = "brcm,brcmstb-memc", "simple-bus";
  188. ranges;
  189. ddr-phy@f1206000 {
  190. compatible = "brcm,brcmstb-ddr-phy-v240.1";
  191. reg = <0xf1206000 0x21c>;
  192. };
  193. shimphy@f1208000 {
  194. compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
  195. reg = <0xf1208000 0xe4>;
  196. };
  197. memc-ddr@f1202000 {
  198. reg = <0xf1202000 0x800>;
  199. compatible = "brcm,brcmstb-memc-ddr";
  200. };
  201. };
  202. };