brcm,stb-avs-cpu-freq.txt 2.5 KB

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  1. Broadcom AVS mail box and interrupt register bindings
  2. =====================================================
  3. A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
  4. references the mailbox register used to communicate with the AVS CPU[1]. The
  5. second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
  6. the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
  7. command sent to it by a driver. Interrupting the AVS CPU is mandatory for
  8. commands to be processed.
  9. The interface also requires a reference to the AVS host interrupt controller,
  10. so a driver can react to interrupts generated by the AVS CPU whenever a command
  11. has been processed. See [2] for more information on the brcm,l2-intc node.
  12. [1] The AVS CPU is an independent co-processor that runs proprietary
  13. firmware. On some SoCs, this firmware supports DFS and DVFS in addition to
  14. Adaptive Voltage Scaling.
  15. [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
  16. Node brcm,avs-cpu-data-mem
  17. --------------------------
  18. Required properties:
  19. - compatible: must include: brcm,avs-cpu-data-mem and
  20. should include: one of brcm,bcm7271-avs-cpu-data-mem or
  21. brcm,bcm7268-avs-cpu-data-mem
  22. - reg: Specifies base physical address and size of the registers.
  23. - interrupts: The interrupt that the AVS CPU will use to interrupt the host
  24. when a command completed.
  25. - interrupt-names: The name of the interrupt used to interrupt the host.
  26. Optional properties:
  27. - None
  28. Node brcm,avs-cpu-l2-intr
  29. -------------------------
  30. Required properties:
  31. - compatible: must include: brcm,avs-cpu-l2-intr and
  32. should include: one of brcm,bcm7271-avs-cpu-l2-intr or
  33. brcm,bcm7268-avs-cpu-l2-intr
  34. - reg: Specifies base physical address and size of the registers.
  35. Optional properties:
  36. - None
  37. Example
  38. =======
  39. avs_host_l2_intc: interrupt-controller@f04d1200 {
  40. #interrupt-cells = <1>;
  41. compatible = "brcm,l2-intc";
  42. interrupt-parent = <&intc>;
  43. reg = <0xf04d1200 0x48>;
  44. interrupt-controller;
  45. interrupts = <0x0 0x19 0x0>;
  46. interrupt-names = "avs";
  47. };
  48. avs-cpu-data-mem@f04c4000 {
  49. compatible = "brcm,bcm7271-avs-cpu-data-mem",
  50. "brcm,avs-cpu-data-mem";
  51. reg = <0xf04c4000 0x60>;
  52. interrupts = <0x1a>;
  53. interrupt-parent = <&avs_host_l2_intc>;
  54. interrupt-names = "sw_intr";
  55. };
  56. avs-cpu-l2-intr@f04d1100 {
  57. compatible = "brcm,bcm7271-avs-cpu-l2-intr",
  58. "brcm,avs-cpu-l2-intr";
  59. reg = <0xf04d1100 0x10>;
  60. };