cdns,dsi.txt 3.0 KB

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  1. Cadence DSI bridge
  2. ==================
  3. The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
  4. Required properties:
  5. - compatible: should be set to "cdns,dsi".
  6. - reg: physical base address and length of the controller's registers.
  7. - interrupts: interrupt line connected to the DSI bridge.
  8. - clocks: DSI bridge clocks.
  9. - clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
  10. - phys: phandle link to the MIPI D-PHY controller.
  11. - phy-names: must contain "dphy".
  12. - #address-cells: must be set to 1.
  13. - #size-cells: must be set to 0.
  14. Optional properties:
  15. - resets: DSI reset lines.
  16. - reset-names: can contain "dsi_p_rst".
  17. Required subnodes:
  18. - ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
  19. 2 ports are available:
  20. * port 0: this port is only needed if some of your DSI devices are
  21. controlled through an external bus like I2C or SPI. Can have at
  22. most 4 endpoints. The endpoint number is directly encoding the
  23. DSI virtual channel used by this device.
  24. * port 1: represents the DPI input.
  25. Other ports will be added later to support the new kind of inputs.
  26. - one subnode per DSI device connected on the DSI bus. Each DSI device should
  27. contain a reg property encoding its virtual channel.
  28. Cadence DPHY
  29. ============
  30. Cadence DPHY block.
  31. Required properties:
  32. - compatible: should be set to "cdns,dphy".
  33. - reg: physical base address and length of the DPHY registers.
  34. - clocks: DPHY reference clocks.
  35. - clock-names: must contain "psm" and "pll_ref".
  36. - #phy-cells: must be set to 0.
  37. Example:
  38. dphy0: dphy@fd0e0000{
  39. compatible = "cdns,dphy";
  40. reg = <0x0 0xfd0e0000 0x0 0x1000>;
  41. clocks = <&psm_clk>, <&pll_ref_clk>;
  42. clock-names = "psm", "pll_ref";
  43. #phy-cells = <0>;
  44. };
  45. dsi0: dsi@fd0c0000 {
  46. compatible = "cdns,dsi";
  47. reg = <0x0 0xfd0c0000 0x0 0x1000>;
  48. clocks = <&pclk>, <&sysclk>;
  49. clock-names = "dsi_p_clk", "dsi_sys_clk";
  50. interrupts = <1>;
  51. phys = <&dphy0>;
  52. phy-names = "dphy";
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. ports {
  56. #address-cells = <1>;
  57. #size-cells = <0>;
  58. port@1 {
  59. reg = <1>;
  60. dsi0_dpi_input: endpoint {
  61. remote-endpoint = <&xxx_dpi_output>;
  62. };
  63. };
  64. };
  65. panel: dsi-dev@0 {
  66. compatible = "<vendor,panel>";
  67. reg = <0>;
  68. };
  69. };
  70. or
  71. dsi0: dsi@fd0c0000 {
  72. compatible = "cdns,dsi";
  73. reg = <0x0 0xfd0c0000 0x0 0x1000>;
  74. clocks = <&pclk>, <&sysclk>;
  75. clock-names = "dsi_p_clk", "dsi_sys_clk";
  76. interrupts = <1>;
  77. phys = <&dphy1>;
  78. phy-names = "dphy";
  79. #address-cells = <1>;
  80. #size-cells = <0>;
  81. ports {
  82. #address-cells = <1>;
  83. #size-cells = <0>;
  84. port@0 {
  85. reg = <0>;
  86. #address-cells = <1>;
  87. #size-cells = <0>;
  88. dsi0_output: endpoint@0 {
  89. reg = <0>;
  90. remote-endpoint = <&dsi_panel_input>;
  91. };
  92. };
  93. port@1 {
  94. reg = <1>;
  95. dsi0_dpi_input: endpoint {
  96. remote-endpoint = <&xxx_dpi_output>;
  97. };
  98. };
  99. };
  100. };
  101. i2c@xxx {
  102. panel: panel@59 {
  103. compatible = "<vendor,panel>";
  104. reg = <0x59>;
  105. port {
  106. dsi_panel_input: endpoint {
  107. remote-endpoint = <&dsi0_output>;
  108. };
  109. };
  110. };
  111. };