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- Synopsys DesignWare HDMI TX Encoder
- ===================================
- This document defines device tree properties for the Synopsys DesignWare HDMI
- TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
- specification by itself but is meant to be referenced by platform-specific
- device tree bindings.
- When referenced from platform device tree bindings the properties defined in
- this document are defined as follows. The platform device tree bindings are
- responsible for defining whether each property is required or optional.
- - reg: Memory mapped base address and length of the DWC HDMI TX registers.
- - reg-io-width: Width of the registers specified by the reg property. The
- value is expressed in bytes and must be equal to 1 or 4 if specified. The
- register width defaults to 1 if the property is not present.
- - interrupts: Reference to the DWC HDMI TX interrupt.
- - clocks: References to all the clocks specified in the clock-names property
- as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
- - clock-names: The DWC HDMI TX uses the following clocks.
- - "iahb" is the bus clock for either AHB and APB (mandatory).
- - "isfr" is the internal register configuration clock (mandatory).
- - "cec" is the HDMI CEC controller main clock (optional).
- - ports: The connectivity of the DWC HDMI TX with the rest of the system is
- expressed in using ports as specified in the device graph bindings defined
- in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
- is platform-specific.
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