exynos5433-decon.txt 2.3 KB

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  1. Device-Tree bindings for Samsung Exynos SoC display controller (DECON)
  2. DECON (Display and Enhancement Controller) is the Display Controller for the
  3. Exynos series of SoCs which transfers the image data from a video memory
  4. buffer to an external LCD interface.
  5. Required properties:
  6. - compatible: value should be one of:
  7. "samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
  8. - reg: physical base address and length of the DECON registers set.
  9. - interrupt-names: should contain the interrupt names depending on mode of work:
  10. video mode: "vsync",
  11. command mode: "lcd_sys",
  12. command mode with software trigger: "lcd_sys", "te".
  13. - interrupts or interrupts-extended: list of interrupt specifiers corresponding
  14. to names privided in interrupt-names, as described in
  15. interrupt-controller/interrupts.txt
  16. - clocks: must include clock specifiers corresponding to entries in the
  17. clock-names property.
  18. - clock-names: list of clock names sorted in the same order as the clocks
  19. property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
  20. "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x",
  21. "aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk",
  22. "sclk_decon_eclk"
  23. - ports: contains a port which is connected to mic node. address-cells and
  24. size-cells must 1 and 0, respectively.
  25. - port: contains an endpoint node which is connected to the endpoint in the mic
  26. node. The reg value muset be 0.
  27. Example:
  28. SoC specific DT entry:
  29. decon: decon@13800000 {
  30. compatible = "samsung,exynos5433-decon";
  31. reg = <0x13800000 0x2104>;
  32. clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
  33. <&cmu_disp CLK_ACLK_XIU_DECON0X>,
  34. <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
  35. <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
  36. <&cmu_disp CLK_ACLK_XIU_DECON1X>,
  37. <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
  38. <&cmu_disp CLK_SCLK_DECON_VCLK>,
  39. <&cmu_disp CLK_SCLK_DECON_ECLK>;
  40. clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x",
  41. "pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x",
  42. "pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk";
  43. interrupt-names = "vsync", "lcd_sys";
  44. interrupts = <0 202 0>, <0 203 0>;
  45. ports {
  46. #address-cells = <1>;
  47. #size-cells = <0>;
  48. port@0 {
  49. reg = <0>;
  50. decon_to_mic: endpoint {
  51. remote-endpoint = <&mic_to_decon>;
  52. };
  53. };
  54. };
  55. };