fsl-imx-drm.txt 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162
  1. Freescale i.MX DRM master device
  2. ================================
  3. The freescale i.MX DRM master device is a virtual device needed to list all
  4. IPU or other display interface nodes that comprise the graphics subsystem.
  5. Required properties:
  6. - compatible: Should be "fsl,imx-display-subsystem"
  7. - ports: Should contain a list of phandles pointing to display interface ports
  8. of IPU devices
  9. example:
  10. display-subsystem {
  11. compatible = "fsl,display-subsystem";
  12. ports = <&ipu_di0>;
  13. };
  14. Freescale i.MX IPUv3
  15. ====================
  16. Required properties:
  17. - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
  18. - imx51
  19. - imx53
  20. - imx6q
  21. - imx6qp
  22. - reg: should be register base and length as documented in the
  23. datasheet
  24. - interrupts: Should contain sync interrupt and error interrupt,
  25. in this order.
  26. - resets: phandle pointing to the system reset controller and
  27. reset line index, see reset/fsl,imx-src.txt for details
  28. Additional required properties for fsl,imx6qp-ipu:
  29. - fsl,prg: phandle to prg node associated with this IPU instance
  30. Optional properties:
  31. - port@[0-3]: Port nodes with endpoint definitions as defined in
  32. Documentation/devicetree/bindings/media/video-interfaces.txt.
  33. Ports 0 and 1 should correspond to CSI0 and CSI1,
  34. ports 2 and 3 should correspond to DI0 and DI1, respectively.
  35. example:
  36. ipu: ipu@18000000 {
  37. #address-cells = <1>;
  38. #size-cells = <0>;
  39. compatible = "fsl,imx53-ipu";
  40. reg = <0x18000000 0x080000000>;
  41. interrupts = <11 10>;
  42. resets = <&src 2>;
  43. ipu_di0: port@2 {
  44. reg = <2>;
  45. ipu_di0_disp0: endpoint {
  46. remote-endpoint = <&display_in>;
  47. };
  48. };
  49. };
  50. Freescale i.MX PRE (Prefetch Resolve Engine)
  51. ============================================
  52. Required properties:
  53. - compatible: should be "fsl,imx6qp-pre"
  54. - reg: should be register base and length as documented in the
  55. datasheet
  56. - clocks : phandle to the PRE axi clock input, as described
  57. in Documentation/devicetree/bindings/clock/clock-bindings.txt and
  58. Documentation/devicetree/bindings/clock/imx6q-clock.txt.
  59. - clock-names: should be "axi"
  60. - interrupts: should contain the PRE interrupt
  61. - fsl,iram: phandle pointing to the mmio-sram device node, that should be
  62. used for the PRE SRAM double buffer.
  63. example:
  64. pre@21c8000 {
  65. compatible = "fsl,imx6qp-pre";
  66. reg = <0x021c8000 0x1000>;
  67. interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
  68. clocks = <&clks IMX6QDL_CLK_PRE0>;
  69. clock-names = "axi";
  70. fsl,iram = <&ocram2>;
  71. };
  72. Freescale i.MX PRG (Prefetch Resolve Gasket)
  73. ============================================
  74. Required properties:
  75. - compatible: should be "fsl,imx6qp-prg"
  76. - reg: should be register base and length as documented in the
  77. datasheet
  78. - clocks : phandles to the PRG ipg and axi clock inputs, as described
  79. in Documentation/devicetree/bindings/clock/clock-bindings.txt and
  80. Documentation/devicetree/bindings/clock/imx6q-clock.txt.
  81. - clock-names: should be "ipg" and "axi"
  82. - fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
  83. PRE as the first entry and the muxable PREs following.
  84. example:
  85. prg@21cc000 {
  86. compatible = "fsl,imx6qp-prg";
  87. reg = <0x021cc000 0x1000>;
  88. clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
  89. <&clks IMX6QDL_CLK_PRG0_AXI>;
  90. clock-names = "ipg", "axi";
  91. fsl,pres = <&pre1>, <&pre2>, <&pre3>;
  92. };
  93. Parallel display support
  94. ========================
  95. Required properties:
  96. - compatible: Should be "fsl,imx-parallel-display"
  97. Optional properties:
  98. - interface-pix-fmt: How this display is connected to the
  99. display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
  100. and "lvds666".
  101. - edid: verbatim EDID data block describing attached display.
  102. - ddc: phandle describing the i2c bus handling the display data
  103. channel
  104. - port@[0-1]: Port nodes with endpoint definitions as defined in
  105. Documentation/devicetree/bindings/media/video-interfaces.txt.
  106. Port 0 is the input port connected to the IPU display interface,
  107. port 1 is the output port connected to a panel.
  108. example:
  109. disp0 {
  110. compatible = "fsl,imx-parallel-display";
  111. edid = [edid-data];
  112. interface-pix-fmt = "rgb24";
  113. port@0 {
  114. reg = <0>;
  115. display_in: endpoint {
  116. remote-endpoint = <&ipu_di0_disp0>;
  117. };
  118. };
  119. port@1 {
  120. reg = <1>;
  121. display_out: endpoint {
  122. remote-endpoint = <&panel_in>;
  123. };
  124. };
  125. };
  126. panel {
  127. ...
  128. port {
  129. panel_in: endpoint {
  130. remote-endpoint = <&display_out>;
  131. };
  132. };
  133. };