edp.txt 1.5 KB

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  1. Qualcomm Technologies Inc. adreno/snapdragon eDP output
  2. Required properties:
  3. - compatible:
  4. * "qcom,mdss-edp"
  5. - reg: Physical base address and length of the registers of controller and PLL
  6. - reg-names: The names of register regions. The following regions are required:
  7. * "edp"
  8. * "pll_base"
  9. - interrupts: The interrupt signal from the eDP block.
  10. - power-domains: Should be <&mmcc MDSS_GDSC>.
  11. - clocks: device clocks
  12. See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
  13. - clock-names: the following clocks are required:
  14. * "core"
  15. * "iface"
  16. * "mdp_core"
  17. * "pixel"
  18. * "link"
  19. - #clock-cells: The value should be 1.
  20. - vdda-supply: phandle to vdda regulator device node
  21. - lvl-vdd-supply: phandle to regulator device node which is used to supply power
  22. to HPD receiving chip
  23. - panel-en-gpios: GPIO pin to supply power to panel.
  24. - panel-hpd-gpios: GPIO pin used for eDP hpd.
  25. Example:
  26. mdss_edp: qcom,mdss_edp@fd923400 {
  27. compatible = "qcom,mdss-edp";
  28. reg-names =
  29. "edp",
  30. "pll_base";
  31. reg = <0xfd923400 0x700>,
  32. <0xfd923a00 0xd4>;
  33. interrupt-parent = <&mdss_mdp>;
  34. interrupts = <12 0>;
  35. power-domains = <&mmcc MDSS_GDSC>;
  36. clock-names =
  37. "core",
  38. "pixel",
  39. "iface",
  40. "link",
  41. "mdp_core";
  42. clocks =
  43. <&mmcc MDSS_EDPAUX_CLK>,
  44. <&mmcc MDSS_EDPPIXEL_CLK>,
  45. <&mmcc MDSS_AHB_CLK>,
  46. <&mmcc MDSS_EDPLINK_CLK>,
  47. <&mmcc MDSS_MDP_CLK>;
  48. #clock-cells = <1>;
  49. vdda-supply = <&pma8084_l12>;
  50. lvl-vdd-supply = <&lvl_vreg>;
  51. panel-en-gpios = <&tlmm 137 0>;
  52. panel-hpd-gpios = <&tlmm 103 0>;
  53. };