snps-dma.txt 2.1 KB

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  1. * Synopsys Designware DMA Controller
  2. Required properties:
  3. - compatible: "snps,dma-spear1340"
  4. - reg: Address range of the DMAC registers
  5. - interrupt: Should contain the DMAC interrupt number
  6. - dma-channels: Number of channels supported by hardware
  7. - dma-requests: Number of DMA request lines supported, up to 16
  8. - dma-masters: Number of AHB masters supported by the controller
  9. - #dma-cells: must be <3>
  10. - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
  11. 1: descending
  12. - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
  13. increase from chan n->0
  14. - block_size: Maximum block size supported by the controller
  15. - data-width: Maximum data width supported by hardware per AHB master
  16. (in bytes, power of 2)
  17. Deprecated properties:
  18. - data_width: Maximum data width supported by hardware per AHB master
  19. (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
  20. Optional properties:
  21. - is_private: The device channels should be marked as private and not for by the
  22. general purpose DMA channel allocator. False if not passed.
  23. - multi-block: Multi block transfers supported by hardware. Array property with
  24. one cell per channel. 0: not supported, 1 (default): supported.
  25. Example:
  26. dmahost: dma@fc000000 {
  27. compatible = "snps,dma-spear1340";
  28. reg = <0xfc000000 0x1000>;
  29. interrupt-parent = <&vic1>;
  30. interrupts = <12>;
  31. dma-channels = <8>;
  32. dma-requests = <16>;
  33. dma-masters = <2>;
  34. #dma-cells = <3>;
  35. chan_allocation_order = <1>;
  36. chan_priority = <1>;
  37. block_size = <0xfff>;
  38. data-width = <8 8>;
  39. };
  40. DMA clients connected to the Designware DMA controller must use the format
  41. described in the dma.txt file, using a four-cell specifier for each channel.
  42. The four cells in order are:
  43. 1. A phandle pointing to the DMA controller
  44. 2. The DMA request line number
  45. 3. Memory master for transfers on allocated channel
  46. 4. Peripheral master for transfers on allocated channel
  47. Example:
  48. serial@e0000000 {
  49. compatible = "arm,pl011", "arm,primecell";
  50. reg = <0xe0000000 0x1000>;
  51. interrupts = <0 35 0x4>;
  52. dmas = <&dmahost 12 0 1>,
  53. <&dmahost 13 1 0>;
  54. dma-names = "rx", "rx";
  55. };