arm,mali-utgard.txt 3.3 KB

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  1. ARM Mali Utgard GPU
  2. ===================
  3. Required properties:
  4. - compatible
  5. * Must be one of the following:
  6. + "arm,mali-300"
  7. + "arm,mali-400"
  8. + "arm,mali-450"
  9. * And, optionally, one of the vendor specific compatible:
  10. + allwinner,sun4i-a10-mali
  11. + allwinner,sun7i-a20-mali
  12. + allwinner,sun8i-h3-mali
  13. + allwinner,sun50i-h5-mali
  14. + amlogic,meson-gxbb-mali
  15. + amlogic,meson-gxl-mali
  16. + rockchip,rk3036-mali
  17. + rockchip,rk3066-mali
  18. + rockchip,rk3188-mali
  19. + rockchip,rk3228-mali
  20. + rockchip,rk3328-mali
  21. + stericsson,db8500-mali
  22. - reg: Physical base address and length of the GPU registers
  23. - interrupts: an entry for each entry in interrupt-names.
  24. See ../interrupt-controller/interrupts.txt for details.
  25. - interrupt-names:
  26. * ppX: Pixel Processor X interrupt (X from 0 to 7)
  27. * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
  28. * pp: Pixel Processor broadcast interrupt (mali-450 only)
  29. * gp: Geometry Processor interrupt
  30. * gpmmu: Geometry Processor MMU interrupt
  31. - clocks: an entry for each entry in clock-names
  32. - clock-names:
  33. * bus: bus clock for the GPU
  34. * core: clock driving the GPU itself
  35. Optional properties:
  36. - interrupt-names and interrupts:
  37. * pmu: Power Management Unit interrupt, if implemented in hardware
  38. - memory-region:
  39. Memory region to allocate from, as defined in
  40. Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
  41. - mali-supply:
  42. Phandle to regulator for the Mali device, as defined in
  43. Documentation/devicetree/bindings/regulator/regulator.txt for details.
  44. - operating-points-v2:
  45. Operating Points for the GPU, as defined in
  46. Documentation/devicetree/bindings/opp/opp.txt
  47. - power-domains:
  48. A power domain consumer specifier as defined in
  49. Documentation/devicetree/bindings/power/power_domain.txt
  50. Vendor-specific bindings
  51. ------------------------
  52. The Mali GPU is integrated very differently from one SoC to
  53. another. In order to accomodate those differences, you have the option
  54. to specify one more vendor-specific compatible, among:
  55. - allwinner,sun4i-a10-mali
  56. Required properties:
  57. * resets: phandle to the reset line for the GPU
  58. - allwinner,sun7i-a20-mali
  59. Required properties:
  60. * resets: phandle to the reset line for the GPU
  61. - allwinner,sun50i-h5-mali
  62. Required properties:
  63. * resets: phandle to the reset line for the GPU
  64. - Rockchip variants:
  65. Required properties:
  66. * resets: phandle to the reset line for the GPU
  67. - stericsson,db8500-mali
  68. Required properties:
  69. * interrupt-names and interrupts:
  70. + combined: combined interrupt of all of the above lines
  71. Example:
  72. mali: gpu@1c40000 {
  73. compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
  74. reg = <0x01c40000 0x10000>;
  75. interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
  76. <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
  77. <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
  78. <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  79. <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
  80. <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
  81. <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
  82. interrupt-names = "gp",
  83. "gpmmu",
  84. "pp0",
  85. "ppmmu0",
  86. "pp1",
  87. "ppmmu1",
  88. "pmu";
  89. clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
  90. clock-names = "bus", "core";
  91. resets = <&ccu RST_BUS_GPU>;
  92. };