nvidia,gk20a.txt 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990
  1. NVIDIA Tegra Graphics Processing Units
  2. Required properties:
  3. - compatible: "nvidia,<gpu>"
  4. Currently recognized values:
  5. - nvidia,gk20a
  6. - nvidia,gm20b
  7. - nvidia,gp10b
  8. - reg: Physical base address and length of the controller's registers.
  9. Must contain two entries:
  10. - first entry for bar0
  11. - second entry for bar1
  12. - interrupts: Must contain an entry for each entry in interrupt-names.
  13. See ../interrupt-controller/interrupts.txt for details.
  14. - interrupt-names: Must include the following entries:
  15. - stall
  16. - nonstall
  17. - vdd-supply: regulator for supply voltage. Only required for GPUs not using
  18. power domains.
  19. - clocks: Must contain an entry for each entry in clock-names.
  20. See ../clocks/clock-bindings.txt for details.
  21. - clock-names: Must include the following entries:
  22. - gpu
  23. - pwr
  24. If the compatible string is "nvidia,gm20b", then the following clock
  25. is also required:
  26. - ref
  27. - resets: Must contain an entry for each entry in reset-names.
  28. See ../reset/reset.txt for details.
  29. - reset-names: Must include the following entries:
  30. - gpu
  31. - power-domains: GPUs that make use of power domains can define this property
  32. instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
  33. Optional properties:
  34. - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
  35. Example for GK20A:
  36. gpu@57000000 {
  37. compatible = "nvidia,gk20a";
  38. reg = <0x0 0x57000000 0x0 0x01000000>,
  39. <0x0 0x58000000 0x0 0x01000000>;
  40. interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
  41. <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
  42. interrupt-names = "stall", "nonstall";
  43. vdd-supply = <&vdd_gpu>;
  44. clocks = <&tegra_car TEGRA124_CLK_GPU>,
  45. <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
  46. clock-names = "gpu", "pwr";
  47. resets = <&tegra_car 184>;
  48. reset-names = "gpu";
  49. iommus = <&mc TEGRA_SWGROUP_GPU>;
  50. };
  51. Example for GM20B:
  52. gpu@57000000 {
  53. compatible = "nvidia,gm20b";
  54. reg = <0x0 0x57000000 0x0 0x01000000>,
  55. <0x0 0x58000000 0x0 0x01000000>;
  56. interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
  57. <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
  58. interrupt-names = "stall", "nonstall";
  59. clocks = <&tegra_car TEGRA210_CLK_GPU>,
  60. <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
  61. <&tegra_car TEGRA210_CLK_PLL_G_REF>;
  62. clock-names = "gpu", "pwr", "ref";
  63. resets = <&tegra_car 184>;
  64. reset-names = "gpu";
  65. iommus = <&mc TEGRA_SWGROUP_GPU>;
  66. };
  67. Example for GP10B:
  68. gpu@17000000 {
  69. compatible = "nvidia,gp10b";
  70. reg = <0x0 0x17000000 0x0 0x1000000>,
  71. <0x0 0x18000000 0x0 0x1000000>;
  72. interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
  73. GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  74. interrupt-names = "stall", "nonstall";
  75. clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
  76. <&bpmp TEGRA186_CLK_GPU>;
  77. clock-names = "gpu", "pwr";
  78. resets = <&bpmp TEGRA186_RESET_GPU>;
  79. reset-names = "gpu";
  80. power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
  81. iommus = <&smmu TEGRA186_SID_GPU>;
  82. };