i2c-stm32.txt 1.8 KB

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  1. * I2C controller embedded in STMicroelectronics STM32 I2C platform
  2. Required properties :
  3. - compatible : Must be one of the following
  4. - "st,stm32f4-i2c"
  5. - "st,stm32f7-i2c"
  6. - reg : Offset and length of the register set for the device
  7. - interrupts : Must contain the interrupt id for I2C event and then the
  8. interrupt id for I2C error.
  9. - resets: Must contain the phandle to the reset controller.
  10. - clocks: Must contain the input clock of the I2C instance.
  11. - A pinctrl state named "default" must be defined to set pins in mode of
  12. operation for I2C transfer
  13. - #address-cells = <1>;
  14. - #size-cells = <0>;
  15. Optional properties :
  16. - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
  17. the default 100 kHz frequency will be used.
  18. For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
  19. 100000 and 400000.
  20. For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported,
  21. possible values are 100000, 400000 and 1000000.
  22. - i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board
  23. (default: 25)
  24. - i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board
  25. (default: 10)
  26. I2C Timings are derived from these 2 values
  27. Example :
  28. i2c@40005400 {
  29. compatible = "st,stm32f4-i2c";
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32. reg = <0x40005400 0x400>;
  33. interrupts = <31>,
  34. <32>;
  35. resets = <&rcc 277>;
  36. clocks = <&rcc 0 149>;
  37. pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
  38. pinctrl-names = "default";
  39. };
  40. i2c@40005400 {
  41. compatible = "st,stm32f7-i2c";
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. reg = <0x40005400 0x400>;
  45. interrupts = <31>,
  46. <32>;
  47. resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
  48. clocks = <&rcc 1 CLK_I2C1>;
  49. pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
  50. pinctrl-names = "default";
  51. };