rockchip-saradc.txt 1.5 KB

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  1. Rockchip Successive Approximation Register (SAR) A/D Converter bindings
  2. Required properties:
  3. - compatible: should be "rockchip,<name>-saradc" or "rockchip,rk3066-tsadc"
  4. - "rockchip,saradc": for rk3188, rk3288
  5. - "rockchip,rk3066-tsadc": for rk3036
  6. - "rockchip,rk3328-saradc", "rockchip,rk3399-saradc": for rk3328
  7. - "rockchip,rk3399-saradc": for rk3399
  8. - "rockchip,rv1108-saradc", "rockchip,rk3399-saradc": for rv1108
  9. - reg: physical base address of the controller and length of memory mapped
  10. region.
  11. - interrupts: The interrupt number to the cpu. The interrupt specifier format
  12. depends on the interrupt controller.
  13. - clocks: Must contain an entry for each entry in clock-names.
  14. - clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for
  15. the peripheral clock.
  16. - vref-supply: The regulator supply ADC reference voltage.
  17. - #io-channel-cells: Should be 1, see ../iio-bindings.txt
  18. Optional properties:
  19. - resets: Must contain an entry for each entry in reset-names if need support
  20. this option. See ../reset/reset.txt for details.
  21. - reset-names: Must include the name "saradc-apb".
  22. Example:
  23. saradc: saradc@2006c000 {
  24. compatible = "rockchip,saradc";
  25. reg = <0x2006c000 0x100>;
  26. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  27. clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
  28. clock-names = "saradc", "apb_pclk";
  29. resets = <&cru SRST_SARADC>;
  30. reset-names = "saradc-apb";
  31. #io-channel-cells = <1>;
  32. vref-supply = <&vcc18>;
  33. };