brcm,bcm6345-l1-intc.txt 1.9 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455
  1. Broadcom BCM6345-style Level 1 interrupt controller
  2. This block is a first level interrupt controller that is typically connected
  3. directly to one of the HW INT lines on each CPU.
  4. Key elements of the hardware design include:
  5. - 32, 64 or 128 incoming level IRQ lines
  6. - Most onchip peripherals are wired directly to an L1 input
  7. - A separate instance of the register set for each CPU, allowing individual
  8. peripheral IRQs to be routed to any CPU
  9. - Contains one or more enable/status word pairs per CPU
  10. - No atomic set/clear operations
  11. - No polarity/level/edge settings
  12. - No FIFO or priority encoder logic; software is expected to read all
  13. 2-4 status words to determine which IRQs are pending
  14. Required properties:
  15. - compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"
  16. - reg: specifies the base physical address and size of the registers;
  17. the number of supported IRQs is inferred from the size argument
  18. - interrupt-controller: identifies the node as an interrupt controller
  19. - #interrupt-cells: specifies the number of cells needed to encode an interrupt
  20. source, should be 1.
  21. - interrupts: specifies the interrupt line(s) in the interrupt-parent controller
  22. node; valid values depend on the type of parent interrupt controller
  23. If multiple reg ranges and interrupt-parent entries are present on an SMP
  24. system, the driver will allow IRQ SMP affinity to be set up through the
  25. /proc/irq/ interface. In the simplest possible configuration, only one
  26. reg range and one interrupt-parent is needed.
  27. The driver operates in native CPU endian by default, there is no support for
  28. specifying an alternative endianness.
  29. Example:
  30. periph_intc: interrupt-controller@10000000 {
  31. compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc";
  32. reg = <0x10000020 0x20>,
  33. <0x10000040 0x20>;
  34. interrupt-controller;
  35. #interrupt-cells = <1>;
  36. interrupt-parent = <&cpu_intc>;
  37. interrupts = <2>, <3>;
  38. };