rockchip,iommu.txt 1.5 KB

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  1. Rockchip IOMMU
  2. ==============
  3. A Rockchip DRM iommu translates io virtual addresses to physical addresses for
  4. its master device. Each slave device is bound to a single master device, and
  5. shares its clocks, power domain and irq.
  6. Required properties:
  7. - compatible : Should be "rockchip,iommu"
  8. - reg : Address space for the configuration registers
  9. - interrupts : Interrupt specifier for the IOMMU instance
  10. - interrupt-names : Interrupt name for the IOMMU instance
  11. - #iommu-cells : Should be <0>. This indicates the iommu is a
  12. "single-master" device, and needs no additional information
  13. to associate with its master device. See:
  14. Documentation/devicetree/bindings/iommu/iommu.txt
  15. - clocks : A list of clocks required for the IOMMU to be accessible by
  16. the host CPU.
  17. - clock-names : Should contain the following:
  18. "iface" - Main peripheral bus clock (PCLK/HCL) (required)
  19. "aclk" - AXI bus clock (required)
  20. Optional properties:
  21. - rockchip,disable-mmu-reset : Don't use the mmu reset operation.
  22. Some mmu instances may produce unexpected results
  23. when the reset operation is used.
  24. Example:
  25. vopl_mmu: iommu@ff940300 {
  26. compatible = "rockchip,iommu";
  27. reg = <0xff940300 0x100>;
  28. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  29. interrupt-names = "vopl_mmu";
  30. clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
  31. clock-names = "aclk", "iface";
  32. #iommu-cells = <0>;
  33. };