imx.txt 1.9 KB

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  1. Freescale i.MX Media Video Device
  2. =================================
  3. Video Media Controller node
  4. ---------------------------
  5. This is the media controller node for video capture support. It is a
  6. virtual device that lists the camera serial interface nodes that the
  7. media device will control.
  8. Required properties:
  9. - compatible : "fsl,imx-capture-subsystem";
  10. - ports : Should contain a list of phandles pointing to camera
  11. sensor interface ports of IPU devices
  12. example:
  13. capture-subsystem {
  14. compatible = "fsl,imx-capture-subsystem";
  15. ports = <&ipu1_csi0>, <&ipu1_csi1>;
  16. };
  17. mipi_csi2 node
  18. --------------
  19. This is the device node for the MIPI CSI-2 Receiver core in the i.MX
  20. SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
  21. combined with a D-PHY core mixed into the same register block. In
  22. addition this device consists of an i.MX-specific "CSI2IPU gasket"
  23. glue logic, also controlled from the same register block. The CSI2IPU
  24. gasket demultiplexes the four virtual channel streams from the host
  25. controller's 32-bit output image bus onto four 16-bit parallel busses
  26. to the i.MX IPU CSIs.
  27. Required properties:
  28. - compatible : "fsl,imx6-mipi-csi2";
  29. - reg : physical base address and length of the register set;
  30. - clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx
  31. (the D-PHY clock), video_27m (D-PHY PLL reference
  32. clock), and eim_podf;
  33. - clock-names : must contain "dphy", "ref", "pix";
  34. - port@* : five port nodes must exist, containing endpoints
  35. connecting to the source and sink devices according to
  36. of_graph bindings. The first port is an input port,
  37. connecting with a MIPI CSI-2 source, and ports 1
  38. through 4 are output ports connecting with parallel
  39. bus sink endpoint nodes and correspond to the four
  40. MIPI CSI-2 virtual channel outputs.
  41. Optional properties:
  42. - interrupts : must contain two level-triggered interrupts,
  43. in order: 100 and 101;