mediatek-jpeg-decoder.txt 1.4 KB

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  1. * Mediatek JPEG Decoder
  2. Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
  3. Required properties:
  4. - compatible : must be one of the following string:
  5. "mediatek,mt8173-jpgdec"
  6. "mediatek,mt2701-jpgdec"
  7. - reg : physical base address of the jpeg decoder registers and length of
  8. memory mapped region.
  9. - interrupts : interrupt number to the interrupt controller.
  10. - clocks: device clocks, see
  11. Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
  12. - clock-names: must contain "jpgdec-smi" and "jpgdec".
  13. - power-domains: a phandle to the power domain, see
  14. Documentation/devicetree/bindings/power/power_domain.txt for details.
  15. - mediatek,larb: must contain the local arbiters in the current Socs, see
  16. Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
  17. for details.
  18. - iommus: should point to the respective IOMMU block with master port as
  19. argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
  20. for details.
  21. Example:
  22. jpegdec: jpegdec@15004000 {
  23. compatible = "mediatek,mt2701-jpgdec";
  24. reg = <0 0x15004000 0 0x1000>;
  25. interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
  26. clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
  27. <&imgsys CLK_IMG_JPGDEC>;
  28. clock-names = "jpgdec-smi",
  29. "jpgdec";
  30. power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
  31. mediatek,larb = <&larb2>;
  32. iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
  33. <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
  34. };