video-interfaces.txt 10.0 KB

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  1. Common bindings for video receiver and transmitter interfaces
  2. General concept
  3. ---------------
  4. Video data pipelines usually consist of external devices, e.g. camera sensors,
  5. controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including
  6. video DMA engines and video data processors.
  7. SoC internal blocks are described by DT nodes, placed similarly to other SoC
  8. blocks. External devices are represented as child nodes of their respective
  9. bus controller nodes, e.g. I2C.
  10. Data interfaces on all video devices are described by their child 'port' nodes.
  11. Configuration of a port depends on other devices participating in the data
  12. transfer and is described by 'endpoint' subnodes.
  13. device {
  14. ...
  15. ports {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. port@0 {
  19. ...
  20. endpoint@0 { ... };
  21. endpoint@1 { ... };
  22. };
  23. port@1 { ... };
  24. };
  25. };
  26. If a port can be configured to work with more than one remote device on the same
  27. bus, an 'endpoint' child node must be provided for each of them. If more than
  28. one port is present in a device node or there is more than one endpoint at a
  29. port, or port node needs to be associated with a selected hardware interface,
  30. a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
  31. used.
  32. All 'port' nodes can be grouped under optional 'ports' node, which allows to
  33. specify #address-cells, #size-cells properties independently for the 'port'
  34. and 'endpoint' nodes and any child device nodes a device might have.
  35. Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
  36. phandles. An endpoint subnode of a device contains all properties needed for
  37. configuration of this device for data exchange with other device. In most
  38. cases properties at the peer 'endpoint' nodes will be identical, however they
  39. might need to be different when there is any signal modifications on the bus
  40. between two devices, e.g. there are logic signal inverters on the lines.
  41. It is allowed for multiple endpoints at a port to be active simultaneously,
  42. where supported by a device. For example, in case where a data interface of
  43. a device is partitioned into multiple data busses, e.g. 16-bit input port
  44. divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
  45. and data-shift properties can be used to assign physical data lines to each
  46. endpoint node (logical bus).
  47. Documenting bindings for devices
  48. --------------------------------
  49. All required and optional bindings the device supports shall be explicitly
  50. documented in device DT binding documentation. This also includes port and
  51. endpoint nodes for the device, including unit-addresses and reg properties where
  52. relevant.
  53. Please also see Documentation/devicetree/bindings/graph.txt .
  54. Required properties
  55. -------------------
  56. If there is more than one 'port' or more than one 'endpoint' node or 'reg'
  57. property is present in port and/or endpoint nodes the following properties
  58. are required in a relevant parent node:
  59. - #address-cells : number of cells required to define port/endpoint
  60. identifier, should be 1.
  61. - #size-cells : should be zero.
  62. Optional properties
  63. -------------------
  64. - flash-leds: An array of phandles, each referring to a flash LED, a sub-node
  65. of the LED driver device node.
  66. - lens-focus: A phandle to the node of the focus lens controller.
  67. - rotation: The device, typically an image sensor, is not mounted upright,
  68. but a number of degrees counter clockwise. Typical values are 0 and 180
  69. (upside down).
  70. Optional endpoint properties
  71. ----------------------------
  72. - remote-endpoint: phandle to an 'endpoint' subnode of a remote device node.
  73. - slave-mode: a boolean property indicating that the link is run in slave mode.
  74. The default when this property is not specified is master mode. In the slave
  75. mode horizontal and vertical synchronization signals are provided to the
  76. slave device (data source) by the master device (data sink). In the master
  77. mode the data source device is also the source of the synchronization signals.
  78. - bus-type: data bus type. Possible values are:
  79. 0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656)
  80. 1 - MIPI CSI-2 C-PHY
  81. 2 - MIPI CSI1
  82. 3 - CCP2
  83. - bus-width: number of data lines actively used, valid for the parallel busses.
  84. - data-shift: on the parallel data busses, if bus-width is used to specify the
  85. number of data lines, data-shift can be used to specify which data lines are
  86. used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.
  87. - hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
  88. - vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
  89. Note, that if HSYNC and VSYNC polarities are not specified, embedded
  90. synchronization may be required, where supported.
  91. - data-active: similar to HSYNC and VSYNC, specifies data line polarity.
  92. - data-enable-active: similar to HSYNC and VSYNC, specifies the data enable
  93. signal polarity.
  94. - field-even-active: field signal level during the even field data transmission.
  95. - pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock
  96. signal.
  97. - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for
  98. LOW/HIGH respectively.
  99. - data-lanes: an array of physical data lane indexes. Position of an entry
  100. determines the logical lane number, while the value of an entry indicates
  101. physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
  102. "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0.
  103. If the hardware does not support lane reordering, monotonically
  104. incremented values shall be used from 0 or 1 onwards, depending on
  105. whether or not there is also a clock lane. This property is valid for
  106. serial busses only (e.g. MIPI CSI-2).
  107. - clock-lanes: an array of physical clock lane indexes. Position of an entry
  108. determines the logical lane number, while the value of an entry indicates
  109. physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;",
  110. which places the clock lane on hardware lane 0. This property is valid for
  111. serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this
  112. array contains only one entry.
  113. - clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous
  114. clock mode.
  115. - link-frequencies: Allowed data bus frequencies. For MIPI CSI-2, for
  116. instance, this is the actual frequency of the bus, not bits per clock per
  117. lane value. An array of 64-bit unsigned integers.
  118. - lane-polarities: an array of polarities of the lanes starting from the clock
  119. lane and followed by the data lanes in the same order as in data-lanes.
  120. Valid values are 0 (normal) and 1 (inverted). The length of the array
  121. should be the combined length of data-lanes and clock-lanes properties.
  122. If the lane-polarities property is omitted, the value must be interpreted
  123. as 0 (normal). This property is valid for serial busses only.
  124. - strobe: Whether the clock signal is used as clock (0) or strobe (1). Used
  125. with CCP2, for instance.
  126. Example
  127. -------
  128. The example snippet below describes two data pipelines. ov772x and imx074 are
  129. camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively.
  130. Both sensors are on the I2C control bus corresponding to the i2c0 controller
  131. node. ov772x sensor is linked directly to the ceu0 video host interface.
  132. imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a
  133. (single) DMA engine writing captured data to memory. ceu0 node has a single
  134. 'port' node which may indicate that at any time only one of the following data
  135. pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
  136. ceu0: ceu@fe910000 {
  137. compatible = "renesas,sh-mobile-ceu";
  138. reg = <0xfe910000 0xa0>;
  139. interrupts = <0x880>;
  140. mclk: master_clock {
  141. compatible = "renesas,ceu-clock";
  142. #clock-cells = <1>;
  143. clock-frequency = <50000000>; /* Max clock frequency */
  144. clock-output-names = "mclk";
  145. };
  146. port {
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. /* Parallel bus endpoint */
  150. ceu0_1: endpoint@1 {
  151. reg = <1>; /* Local endpoint # */
  152. remote = <&ov772x_1_1>; /* Remote phandle */
  153. bus-width = <8>; /* Used data lines */
  154. data-shift = <2>; /* Lines 9:2 are used */
  155. /* If hsync-active/vsync-active are missing,
  156. embedded BT.656 sync is used */
  157. hsync-active = <0>; /* Active low */
  158. vsync-active = <0>; /* Active low */
  159. data-active = <1>; /* Active high */
  160. pclk-sample = <1>; /* Rising */
  161. };
  162. /* MIPI CSI-2 bus endpoint */
  163. ceu0_0: endpoint@0 {
  164. reg = <0>;
  165. remote = <&csi2_2>;
  166. };
  167. };
  168. };
  169. i2c0: i2c@fff20000 {
  170. ...
  171. ov772x_1: camera@21 {
  172. compatible = "ovti,ov772x";
  173. reg = <0x21>;
  174. vddio-supply = <&regulator1>;
  175. vddcore-supply = <&regulator2>;
  176. clock-frequency = <20000000>;
  177. clocks = <&mclk 0>;
  178. clock-names = "xclk";
  179. port {
  180. /* With 1 endpoint per port no need for addresses. */
  181. ov772x_1_1: endpoint {
  182. bus-width = <8>;
  183. remote-endpoint = <&ceu0_1>;
  184. hsync-active = <1>;
  185. vsync-active = <0>; /* Who came up with an
  186. inverter here ?... */
  187. data-active = <1>;
  188. pclk-sample = <1>;
  189. };
  190. };
  191. };
  192. imx074: camera@1a {
  193. compatible = "sony,imx074";
  194. reg = <0x1a>;
  195. vddio-supply = <&regulator1>;
  196. vddcore-supply = <&regulator2>;
  197. clock-frequency = <30000000>; /* Shared clock with ov772x_1 */
  198. clocks = <&mclk 0>;
  199. clock-names = "sysclk"; /* Assuming this is the
  200. name in the datasheet */
  201. port {
  202. imx074_1: endpoint {
  203. clock-lanes = <0>;
  204. data-lanes = <1 2>;
  205. remote-endpoint = <&csi2_1>;
  206. };
  207. };
  208. };
  209. };
  210. csi2: csi2@ffc90000 {
  211. compatible = "renesas,sh-mobile-csi2";
  212. reg = <0xffc90000 0x1000>;
  213. interrupts = <0x17a0>;
  214. #address-cells = <1>;
  215. #size-cells = <0>;
  216. port@1 {
  217. compatible = "renesas,csi2c"; /* One of CSI2I and CSI2C. */
  218. reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S,
  219. PHY_M has port address 0,
  220. is unused. */
  221. csi2_1: endpoint {
  222. clock-lanes = <0>;
  223. data-lanes = <2 1>;
  224. remote-endpoint = <&imx074_1>;
  225. };
  226. };
  227. port@2 {
  228. reg = <2>; /* port 2: link to the CEU */
  229. csi2_2: endpoint {
  230. remote-endpoint = <&ceu0_0>;
  231. };
  232. };
  233. };