soc.txt 4.3 KB

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  1. * Broadcom cable/DSL/settop platforms
  2. Required properties:
  3. - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
  4. "brcm,bcm3384-viper", "brcm,bcm33843-viper"
  5. "brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6362", "brcm,bcm6368",
  6. "brcm,bcm63168", "brcm,bcm63268",
  7. "brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360",
  8. "brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425"
  9. The experimental -viper variants are for running Linux on the 3384's
  10. BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
  11. Power management
  12. ----------------
  13. For power management (particularly, S2/S3/S5 system suspend), the following SoC
  14. components are needed:
  15. = Always-On control block (AON CTRL)
  16. This hardware provides control registers for the "always-on" (even in low-power
  17. modes) hardware, such as the Power Management State Machine (PMSM).
  18. Required properties:
  19. - compatible : should be one of
  20. "brcm,bcm7425-aon-ctrl"
  21. "brcm,bcm7429-aon-ctrl"
  22. "brcm,bcm7435-aon-ctrl" and
  23. "brcm,brcmstb-aon-ctrl"
  24. - reg : the register start and length for the AON CTRL block
  25. Example:
  26. syscon@410000 {
  27. compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
  28. reg = <0x410000 0x400>;
  29. };
  30. = Memory controllers
  31. A Broadcom STB SoC typically has a number of independent memory controllers,
  32. each of which may have several associated hardware blocks, which are versioned
  33. independently (control registers, DDR PHYs, etc.). One might consider
  34. describing these controllers as a parent "memory controllers" block, which
  35. contains N sub-nodes (one for each controller in the system), each of which is
  36. associated with a number of hardware register resources (e.g., its PHY.
  37. == MEMC (MEMory Controller)
  38. Represents a single memory controller instance.
  39. Required properties:
  40. - compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
  41. - ranges : should contain the child address in the parent address
  42. space, must be 0 here, and the register start and length of
  43. the entire memory controller (including all sub nodes: DDR PHY,
  44. arbiter, etc.)
  45. - #address-cells : must be 1
  46. - #size-cells : must be 1
  47. Example:
  48. memory-controller@0 {
  49. compatible = "brcm,brcmstb-memc", "simple-bus";
  50. ranges = <0x0 0x0 0xa000>;
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. memc-arb@1000 {
  54. ...
  55. };
  56. memc-ddr@2000 {
  57. ...
  58. };
  59. ddr-phy@6000 {
  60. ...
  61. };
  62. };
  63. Should contain subnodes for any of the following relevant hardware resources:
  64. == DDR PHY control
  65. Control registers for this memory controller's DDR PHY.
  66. Required properties:
  67. - compatible : should contain one of these
  68. "brcm,brcmstb-ddr-phy-v64.5"
  69. "brcm,brcmstb-ddr-phy"
  70. - reg : the DDR PHY register range and length
  71. Example:
  72. ddr-phy@6000 {
  73. compatible = "brcm,brcmstb-ddr-phy-v64.5";
  74. reg = <0x6000 0xc8>;
  75. };
  76. == DDR memory controller sequencer
  77. Control registers for this memory controller's DDR memory sequencer
  78. Required properties:
  79. - compatible : should contain one of these
  80. "brcm,bcm7425-memc-ddr"
  81. "brcm,bcm7429-memc-ddr"
  82. "brcm,bcm7435-memc-ddr" and
  83. "brcm,brcmstb-memc-ddr"
  84. - reg : the DDR sequencer register range and length
  85. Example:
  86. memc-ddr@2000 {
  87. compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr";
  88. reg = <0x2000 0x300>;
  89. };
  90. == MEMC Arbiter
  91. The memory controller arbiter is responsible for memory clients allocation
  92. (bandwidth, priorities etc.) and needs to have its contents restored during
  93. deep sleep states (S3).
  94. Required properties:
  95. - compatible : should contain one of these
  96. "brcm,brcmstb-memc-arb-v10.0.0.0"
  97. "brcm,brcmstb-memc-arb"
  98. - reg : the DDR Arbiter register range and length
  99. Example:
  100. memc-arb@1000 {
  101. compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";
  102. reg = <0x1000 0x248>;
  103. };
  104. == Timers
  105. The Broadcom STB chips contain a timer block with several general purpose
  106. timers that can be used.
  107. Required properties:
  108. - compatible : should contain one of:
  109. "brcm,bcm7425-timers"
  110. "brcm,bcm7429-timers"
  111. "brcm,bcm7435-timers" and
  112. "brcm,brcmstb-timers"
  113. - reg : the timers register range
  114. - interrupts : the interrupt line for this timer block
  115. Example:
  116. timers: timer@4067c0 {
  117. compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";
  118. reg = <0x4067c0 0x40>;
  119. interrupts = <&periph_intc 19>;
  120. };