arasan,sdhci.txt 3.1 KB

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  1. Device Tree Bindings for the Arasan SDHCI Controller
  2. The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
  3. Only deviations are documented here.
  4. [1] Documentation/devicetree/bindings/mmc/mmc.txt
  5. [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
  6. [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
  7. [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
  8. Required Properties:
  9. - compatible: Compatibility string. One of:
  10. - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
  11. - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
  12. - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
  13. - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
  14. For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  15. - reg: From mmc bindings: Register location and length.
  16. - clocks: From clock bindings: Handles to clock inputs.
  17. - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
  18. - interrupts: Interrupt specifier
  19. Required Properties for "arasan,sdhci-5.1":
  20. - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
  21. - phy-names: MUST be "phy_arasan".
  22. Optional Properties:
  23. - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
  24. used to access core corecfg registers. Offsets of registers in this
  25. syscon are determined based on the main compatible string for the device.
  26. - clock-output-names: If specified, this will be the name of the card clock
  27. which will be exposed by this device. Required if #clock-cells is
  28. specified.
  29. - #clock-cells: If specified this should be the value <0>. With this property
  30. in place we will export a clock representing the Card Clock. This clock
  31. is expected to be consumed by our PHY. You must also specify
  32. - xlnx,fails-without-test-cd: when present, the controller doesn't work when
  33. the CD line is not connected properly, and the line is not connected
  34. properly. Test mode can be used to force the controller to function.
  35. - xlnx,int-clock-stable-broken: when present, the controller always reports
  36. that the internal clock is stable even when it is not.
  37. Example:
  38. sdhci@e0100000 {
  39. compatible = "arasan,sdhci-8.9a";
  40. reg = <0xe0100000 0x1000>;
  41. clock-names = "clk_xin", "clk_ahb";
  42. clocks = <&clkc 21>, <&clkc 32>;
  43. interrupt-parent = <&gic>;
  44. interrupts = <0 24 4>;
  45. } ;
  46. sdhci@e2800000 {
  47. compatible = "arasan,sdhci-5.1";
  48. reg = <0xe2800000 0x1000>;
  49. clock-names = "clk_xin", "clk_ahb";
  50. clocks = <&cru 8>, <&cru 18>;
  51. interrupt-parent = <&gic>;
  52. interrupts = <0 24 4>;
  53. phys = <&emmc_phy>;
  54. phy-names = "phy_arasan";
  55. } ;
  56. sdhci: sdhci@fe330000 {
  57. compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
  58. reg = <0x0 0xfe330000 0x0 0x10000>;
  59. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  60. clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
  61. clock-names = "clk_xin", "clk_ahb";
  62. arasan,soc-ctl-syscon = <&grf>;
  63. assigned-clocks = <&cru SCLK_EMMC>;
  64. assigned-clock-rates = <200000000>;
  65. clock-output-names = "emmc_cardclock";
  66. phys = <&emmc_phy>;
  67. phy-names = "phy_arasan";
  68. #clock-cells = <0>;
  69. };