mmc.txt 7.4 KB

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  1. These properties are common to multiple MMC host controllers. Any host
  2. that requires the respective functionality should implement them using
  3. these definitions.
  4. Interpreted by the OF core:
  5. - reg: Registers location and length.
  6. - interrupts: Interrupts used by the MMC controller.
  7. Card detection:
  8. If no property below is supplied, host native card detect is used.
  9. Only one of the properties in this section should be supplied:
  10. - broken-cd: There is no card detection available; polling must be used.
  11. - cd-gpios: Specify GPIOs for card detection, see gpio binding
  12. - non-removable: non-removable slot (like eMMC); assume always present.
  13. Optional properties:
  14. - bus-width: Number of data lines, can be <1>, <4>, or <8>. The default
  15. will be <1> if the property is absent.
  16. - wp-gpios: Specify GPIOs for write protection, see gpio binding
  17. - cd-inverted: when present, polarity on the CD line is inverted. See the note
  18. below for the case, when a GPIO is used for the CD line
  19. - cd-debounce-delay-ms: Set delay time before detecting card after card insert interrupt.
  20. It's only valid when cd-gpios is present.
  21. - wp-inverted: when present, polarity on the WP line is inverted. See the note
  22. below for the case, when a GPIO is used for the WP line
  23. - disable-wp: When set no physical WP line is present. This property should
  24. only be specified when the controller has a dedicated write-protect
  25. detection logic. If a GPIO is always used for the write-protect detection
  26. logic it is sufficient to not specify wp-gpios property in the absence of a WP
  27. line.
  28. - max-frequency: maximum operating clock frequency
  29. - no-1-8-v: when present, denotes that 1.8v card voltage is not supported on
  30. this system, even if the controller claims it is.
  31. - cap-sd-highspeed: SD high-speed timing is supported
  32. - cap-mmc-highspeed: MMC high-speed timing is supported
  33. - sd-uhs-sdr12: SD UHS SDR12 speed is supported
  34. - sd-uhs-sdr25: SD UHS SDR25 speed is supported
  35. - sd-uhs-sdr50: SD UHS SDR50 speed is supported
  36. - sd-uhs-sdr104: SD UHS SDR104 speed is supported
  37. - sd-uhs-ddr50: SD UHS DDR50 speed is supported
  38. - cap-power-off-card: powering off the card is safe
  39. - cap-mmc-hw-reset: eMMC hardware reset is supported
  40. - cap-sdio-irq: enable SDIO IRQ signalling on this interface
  41. - full-pwr-cycle: full power cycle of the card is supported
  42. - mmc-ddr-3_3v: eMMC high-speed DDR mode(3.3V I/O) is supported
  43. - mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
  44. - mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
  45. - mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
  46. - mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
  47. - mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
  48. - mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
  49. - mmc-hs400-enhanced-strobe: eMMC HS400 enhanced strobe mode is supported
  50. - dsr: Value the card's (optional) Driver Stage Register (DSR) should be
  51. programmed with. Valid range: [0 .. 0xffff].
  52. - no-sdio: controller is limited to send sdio cmd during initialization
  53. - no-sd: controller is limited to send sd cmd during initialization
  54. - no-mmc: controller is limited to send mmc cmd during initialization
  55. - fixed-emmc-driver-type: for non-removable eMMC, enforce this driver type.
  56. The value <n> is the driver type as specified in the eMMC specification
  57. (table 206 in spec version 5.1).
  58. - post-power-on-delay-ms : It was invented for MMC pwrseq-simple which could
  59. be referred to mmc-pwrseq-simple.txt. But now it's reused as a tunable delay
  60. waiting for I/O signalling and card power supply to be stable, regardless of
  61. whether pwrseq-simple is used. Default to 10ms if no available.
  62. - supports-cqe : The presence of this property indicates that the corresponding
  63. MMC host controller supports HW command queue feature.
  64. - disable-cqe-dcmd: This property indicates that the MMC controller's command
  65. queue engine (CQE) does not support direct commands (DCMDs).
  66. *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
  67. polarity properties, we have to fix the meaning of the "normal" and "inverted"
  68. line levels. We choose to follow the SDHCI standard, which specifies both those
  69. lines as "active low." Therefore, using the "cd-inverted" property means, that
  70. the CD line is active high, i.e. it is high, when a card is inserted. Similar
  71. logic applies to the "wp-inverted" property.
  72. CD and WP lines can be implemented on the hardware in one of two ways: as GPIOs,
  73. specified in cd-gpios and wp-gpios properties, or as dedicated pins. Polarity of
  74. dedicated pins can be specified, using *-inverted properties. GPIO polarity can
  75. also be specified using the GPIO_ACTIVE_LOW flag. This creates an ambiguity
  76. in the latter case. We choose to use the XOR logic for GPIO CD and WP lines.
  77. This means, the two properties are "superimposed," for example leaving the
  78. GPIO_ACTIVE_LOW flag clear and specifying the respective *-inverted property
  79. property results in a double-inversion and actually means the "normal" line
  80. polarity is in effect.
  81. Optional SDIO properties:
  82. - keep-power-in-suspend: Preserves card power during a suspend/resume cycle
  83. - wakeup-source: Enables wake up of host system on SDIO IRQ assertion
  84. (Legacy property supported: "enable-sdio-wakeup")
  85. MMC power
  86. ---------
  87. Controllers may implement power control from both the connected cards and
  88. the IO signaling (for example to change to high-speed 1.8V signalling). If
  89. the system supports this, then the following two properties should point
  90. to valid regulator nodes:
  91. - vqmmc-supply: supply node for IO line power
  92. - vmmc-supply: supply node for card's power
  93. MMC power sequences:
  94. --------------------
  95. System on chip designs may specify a specific MMC power sequence. To
  96. successfully detect an (e)MMC/SD/SDIO card, that power sequence must be
  97. maintained while initializing the card.
  98. Optional property:
  99. - mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*"
  100. for documentation of MMC power sequence bindings.
  101. Use of Function subnodes
  102. ------------------------
  103. On embedded systems the cards connected to a host may need additional
  104. properties. These can be specified in subnodes to the host controller node.
  105. The subnodes are identified by the standard 'reg' property.
  106. Which information exactly can be specified depends on the bindings for the
  107. SDIO function driver for the subnode, as specified by the compatible string.
  108. Required host node properties when using function subnodes:
  109. - #address-cells: should be one. The cell is the slot id.
  110. - #size-cells: should be zero.
  111. Required function subnode properties:
  112. - reg: Must contain the SDIO function number of the function this subnode
  113. describes. A value of 0 denotes the memory SD function, values from
  114. 1 to 7 denote the SDIO functions.
  115. Optional function subnode properties:
  116. - compatible: name of SDIO function following generic names recommended practice
  117. Examples
  118. --------
  119. Basic example:
  120. sdhci@ab000000 {
  121. compatible = "sdhci";
  122. reg = <0xab000000 0x200>;
  123. interrupts = <23>;
  124. bus-width = <4>;
  125. cd-gpios = <&gpio 69 0>;
  126. cd-inverted;
  127. wp-gpios = <&gpio 70 0>;
  128. max-frequency = <50000000>;
  129. keep-power-in-suspend;
  130. wakeup-source;
  131. mmc-pwrseq = <&sdhci0_pwrseq>
  132. }
  133. Example with sdio function subnode:
  134. mmc3: mmc@1c12000 {
  135. #address-cells = <1>;
  136. #size-cells = <0>;
  137. pinctrl-names = "default";
  138. pinctrl-0 = <&mmc3_pins_a>;
  139. vmmc-supply = <&reg_vmmc3>;
  140. bus-width = <4>;
  141. non-removable;
  142. mmc-pwrseq = <&sdhci0_pwrseq>
  143. brcmf: bcrmf@1 {
  144. reg = <1>;
  145. compatible = "brcm,bcm43xx-fmac";
  146. interrupt-parent = <&pio>;
  147. interrupts = <10 8>; /* PH10 / EINT10 */
  148. interrupt-names = "host-wake";
  149. };
  150. };