microchip,enc28j60.txt 2.3 KB

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  1. * Microchip ENC28J60
  2. This is a standalone 10 MBit ethernet controller with SPI interface.
  3. For each device connected to a SPI bus, define a child node within
  4. the SPI master node.
  5. Required properties:
  6. - compatible: Should be "microchip,enc28j60"
  7. - reg: Specify the SPI chip select the ENC28J60 is wired to
  8. - interrupts: Specify the interrupt index within the interrupt controller (referred
  9. to above in interrupt-parent) and interrupt type. The ENC28J60 natively
  10. generates falling edge interrupts, however, additional board logic
  11. might invert the signal.
  12. - pinctrl-names: List of assigned state names, see pinctrl binding documentation.
  13. - pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
  14. see also generic and your platform specific pinctrl binding
  15. documentation.
  16. Optional properties:
  17. - spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60.
  18. According to the ENC28J80 datasheet, the chip allows a maximum of 20 MHz, however,
  19. board designs may need to limit this value.
  20. - local-mac-address: See ethernet.txt in the same directory.
  21. Example (for NXP i.MX28 with pin control stuff for GPIO irq):
  22. ssp2: ssp@80014000 {
  23. compatible = "fsl,imx28-spi";
  24. pinctrl-names = "default";
  25. pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>;
  26. enc28j60: ethernet@0 {
  27. compatible = "microchip,enc28j60";
  28. pinctrl-names = "default";
  29. pinctrl-0 = <&enc28j60_pins>;
  30. reg = <0>;
  31. interrupt-parent = <&gpio3>;
  32. interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  33. spi-max-frequency = <12000000>;
  34. };
  35. };
  36. pinctrl@80018000 {
  37. enc28j60_pins: enc28j60_pins@0 {
  38. reg = <0>;
  39. fsl,pinmux-ids = <
  40. MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */
  41. >;
  42. fsl,drive-strength = <MXS_DRIVE_4mA>;
  43. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  44. fsl,pull-up = <MXS_PULL_DISABLE>;
  45. };
  46. };