qcom,ath10k.txt 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152
  1. * Qualcomm Atheros ath10k wireless devices
  2. Required properties:
  3. - compatible: Should be one of the following:
  4. * "qcom,ath10k"
  5. * "qcom,ipq4019-wifi"
  6. * "qcom,wcn3990-wifi"
  7. PCI based devices uses compatible string "qcom,ath10k" and takes calibration
  8. data along with board specific data via "qcom,ath10k-calibration-data".
  9. Rest of the properties are not applicable for PCI based devices.
  10. AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
  11. and also uses most of the properties defined in this doc (except
  12. "qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
  13. to carry pre calibration data.
  14. In general, entry "qcom,ath10k-pre-calibration-data" and
  15. "qcom,ath10k-calibration-data" conflict with each other and only one
  16. can be provided per device.
  17. SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi".
  18. Optional properties:
  19. - reg: Address and length of the register set for the device.
  20. - reg-names: Must include the list of following reg names,
  21. "membase"
  22. - resets: Must contain an entry for each entry in reset-names.
  23. See ../reset/reseti.txt for details.
  24. - reset-names: Must include the list of following reset names,
  25. "wifi_cpu_init"
  26. "wifi_radio_srif"
  27. "wifi_radio_warm"
  28. "wifi_radio_cold"
  29. "wifi_core_warm"
  30. "wifi_core_cold"
  31. - clocks: List of clock specifiers, must contain an entry for each required
  32. entry in clock-names.
  33. - clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref",
  34. "wifi_wcss_rtc".
  35. - interrupts: List of interrupt lines. Must contain an entry
  36. for each entry in the interrupt-names property.
  37. - interrupt-names: Must include the entries for MSI interrupt
  38. names ("msi0" to "msi15") and legacy interrupt
  39. name ("legacy"),
  40. - qcom,msi_addr: MSI interrupt address.
  41. - qcom,msi_base: Base value to add before writing MSI data into
  42. MSI address register.
  43. - qcom,ath10k-calibration-variant: string to search for in the board-2.bin
  44. variant list with the same bus and device
  45. specific ids
  46. - qcom,ath10k-calibration-data : calibration data + board specific data
  47. as an array, the length can vary between
  48. hw versions.
  49. - qcom,ath10k-pre-calibration-data : pre calibration data as an array,
  50. the length can vary between hw versions.
  51. - <supply-name>-supply: handle to the regulator device tree node
  52. optional "supply-name" is "vdd-0.8-cx-mx".
  53. Example (to supply the calibration data alone):
  54. In this example, the node is defined as child node of the PCI controller.
  55. pci {
  56. pcie@0 {
  57. reg = <0 0 0 0 0>;
  58. #interrupt-cells = <1>;
  59. #size-cells = <2>;
  60. #address-cells = <3>;
  61. device_type = "pci";
  62. ath10k@0,0 {
  63. reg = <0 0 0 0 0>;
  64. device_type = "pci";
  65. qcom,ath10k-calibration-data = [ 01 02 03 ... ];
  66. };
  67. };
  68. };
  69. Example (to supply ipq4019 SoC wifi block details):
  70. wifi0: wifi@a000000 {
  71. compatible = "qcom,ipq4019-wifi";
  72. reg = <0xa000000 0x200000>;
  73. resets = <&gcc WIFI0_CPU_INIT_RESET>,
  74. <&gcc WIFI0_RADIO_SRIF_RESET>,
  75. <&gcc WIFI0_RADIO_WARM_RESET>,
  76. <&gcc WIFI0_RADIO_COLD_RESET>,
  77. <&gcc WIFI0_CORE_WARM_RESET>,
  78. <&gcc WIFI0_CORE_COLD_RESET>;
  79. reset-names = "wifi_cpu_init",
  80. "wifi_radio_srif",
  81. "wifi_radio_warm",
  82. "wifi_radio_cold",
  83. "wifi_core_warm",
  84. "wifi_core_cold";
  85. clocks = <&gcc GCC_WCSS2G_CLK>,
  86. <&gcc GCC_WCSS2G_REF_CLK>,
  87. <&gcc GCC_WCSS2G_RTC_CLK>;
  88. clock-names = "wifi_wcss_cmd",
  89. "wifi_wcss_ref",
  90. "wifi_wcss_rtc";
  91. interrupts = <0 0x20 0x1>,
  92. <0 0x21 0x1>,
  93. <0 0x22 0x1>,
  94. <0 0x23 0x1>,
  95. <0 0x24 0x1>,
  96. <0 0x25 0x1>,
  97. <0 0x26 0x1>,
  98. <0 0x27 0x1>,
  99. <0 0x28 0x1>,
  100. <0 0x29 0x1>,
  101. <0 0x2a 0x1>,
  102. <0 0x2b 0x1>,
  103. <0 0x2c 0x1>,
  104. <0 0x2d 0x1>,
  105. <0 0x2e 0x1>,
  106. <0 0x2f 0x1>,
  107. <0 0xa8 0x0>;
  108. interrupt-names = "msi0", "msi1", "msi2", "msi3",
  109. "msi4", "msi5", "msi6", "msi7",
  110. "msi8", "msi9", "msi10", "msi11",
  111. "msi12", "msi13", "msi14", "msi15",
  112. "legacy";
  113. qcom,msi_addr = <0x0b006040>;
  114. qcom,msi_base = <0x40>;
  115. qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ];
  116. };
  117. Example (to supply wcn3990 SoC wifi block details):
  118. wifi@18000000 {
  119. compatible = "qcom,wcn3990-wifi";
  120. reg = <0x18800000 0x800000>;
  121. reg-names = "membase";
  122. clocks = <&clock_gcc clk_aggre2_noc_clk>;
  123. clock-names = "smmu_aggre2_noc_clk"
  124. interrupts =
  125. <0 130 0 /* CE0 */ >,
  126. <0 131 0 /* CE1 */ >,
  127. <0 132 0 /* CE2 */ >,
  128. <0 133 0 /* CE3 */ >,
  129. <0 134 0 /* CE4 */ >,
  130. <0 135 0 /* CE5 */ >,
  131. <0 136 0 /* CE6 */ >,
  132. <0 137 0 /* CE7 */ >,
  133. <0 138 0 /* CE8 */ >,
  134. <0 139 0 /* CE9 */ >,
  135. <0 140 0 /* CE10 */ >,
  136. <0 141 0 /* CE11 */ >;
  137. vdd-0.8-cx-mx-supply = <&pm8998_l5>;
  138. };