designware-pcie.txt 2.4 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970
  1. * Synopsys DesignWare PCIe interface
  2. Required properties:
  3. - compatible:
  4. "snps,dw-pcie" for RC mode;
  5. "snps,dw-pcie-ep" for EP mode;
  6. - reg: Should contain the configuration address space.
  7. - reg-names: Must be "config" for the PCIe configuration space.
  8. (The old way of getting the configuration address space from "ranges"
  9. is deprecated and should be avoided.)
  10. - num-lanes: number of lanes to use
  11. RC mode:
  12. - #address-cells: set to <3>
  13. - #size-cells: set to <2>
  14. - device_type: set to "pci"
  15. - ranges: ranges for the PCI memory and I/O regions
  16. - #interrupt-cells: set to <1>
  17. - interrupt-map-mask and interrupt-map: standard PCI
  18. properties to define the mapping of the PCIe interface to interrupt
  19. numbers.
  20. EP mode:
  21. - num-ib-windows: number of inbound address translation windows
  22. - num-ob-windows: number of outbound address translation windows
  23. Optional properties:
  24. - num-lanes: number of lanes to use (this property should be specified unless
  25. the link is brought already up in BIOS)
  26. - reset-gpio: GPIO pin number of power good signal
  27. - clocks: Must contain an entry for each entry in clock-names.
  28. See ../clocks/clock-bindings.txt for details.
  29. - clock-names: Must include the following entries:
  30. - "pcie"
  31. - "pcie_bus"
  32. RC mode:
  33. - num-viewport: number of view ports configured in hardware. If a platform
  34. does not specify it, the driver assumes 2.
  35. - bus-range: PCI bus numbers covered (it is recommended for new devicetrees
  36. to specify this property, to keep backwards compatibility a range of
  37. 0x00-0xff is assumed if not present)
  38. EP mode:
  39. - max-functions: maximum number of functions that can be configured
  40. Example configuration:
  41. pcie: pcie@dfc00000 {
  42. compatible = "snps,dw-pcie";
  43. reg = <0xdfc00000 0x0001000>, /* IP registers */
  44. <0xd0000000 0x0002000>; /* Configuration space */
  45. reg-names = "dbi", "config";
  46. #address-cells = <3>;
  47. #size-cells = <2>;
  48. device_type = "pci";
  49. ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
  50. 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
  51. interrupts = <25>, <24>;
  52. #interrupt-cells = <1>;
  53. num-lanes = <1>;
  54. };
  55. or
  56. pcie: pcie@dfc00000 {
  57. compatible = "snps,dw-pcie-ep";
  58. reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
  59. <0xdfc01000 0x0001000>, /* IP registers 2 */
  60. <0xd0000000 0x2000000>; /* Configuration space */
  61. reg-names = "dbi", "dbi2", "addr_space";
  62. num-ib-windows = <6>;
  63. num-ob-windows = <2>;
  64. num-lanes = <1>;
  65. };