phy-hisi-inno-usb2.txt 2.0 KB

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  1. Device tree bindings for HiSilicon INNO USB2 PHY
  2. Required properties:
  3. - compatible: Should be one of the following strings:
  4. "hisilicon,inno-usb2-phy",
  5. "hisilicon,hi3798cv200-usb2-phy".
  6. - reg: Should be the address space for PHY configuration register in peripheral
  7. controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
  8. - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
  9. reference clock.
  10. - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
  11. signal.
  12. - #address-cells: Must be 1.
  13. - #size-cells: Must be 0.
  14. The INNO USB2 PHY device should be a child node of peripheral controller that
  15. contains the PHY configuration register, and each device suppports up to 2 PHY
  16. ports which are represented as child nodes of INNO USB2 PHY device.
  17. Required properties for PHY port node:
  18. - reg: The PHY port instance number.
  19. - #phy-cells: Defined by generic PHY bindings. Must be 0.
  20. - resets: The phandle and reset specifier pair for PHY port reset signal.
  21. Refer to phy/phy-bindings.txt for the generic PHY binding properties
  22. Example:
  23. perictrl: peripheral-controller@8a20000 {
  24. compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
  25. reg = <0x8a20000 0x1000>;
  26. #address-cells = <1>;
  27. #size-cells = <1>;
  28. ranges = <0x0 0x8a20000 0x1000>;
  29. usb2_phy1: usb2-phy@120 {
  30. compatible = "hisilicon,hi3798cv200-usb2-phy";
  31. reg = <0x120 0x4>;
  32. clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
  33. resets = <&crg 0xbc 4>;
  34. #address-cells = <1>;
  35. #size-cells = <0>;
  36. usb2_phy1_port0: phy@0 {
  37. reg = <0>;
  38. #phy-cells = <0>;
  39. resets = <&crg 0xbc 8>;
  40. };
  41. usb2_phy1_port1: phy@1 {
  42. reg = <1>;
  43. #phy-cells = <0>;
  44. resets = <&crg 0xbc 9>;
  45. };
  46. };
  47. usb2_phy2: usb2-phy@124 {
  48. compatible = "hisilicon,hi3798cv200-usb2-phy";
  49. reg = <0x124 0x4>;
  50. clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
  51. resets = <&crg 0xbc 6>;
  52. #address-cells = <1>;
  53. #size-cells = <0>;
  54. usb2_phy2_port0: phy@0 {
  55. reg = <0>;
  56. #phy-cells = <0>;
  57. resets = <&crg 0xbc 10>;
  58. };
  59. };
  60. };