123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657 |
- Socionext UniPhier Regulator Controller
- This describes the devicetree bindings for regulator controller implemented
- on Socionext UniPhier SoCs.
- USB3 Controller
- ---------------
- This regulator controls VBUS and belongs to USB3 glue layer. Before using
- the regulator, it is necessary to control the clocks and resets to enable
- this layer. These clocks and resets should be described in each property.
- Required properties:
- - compatible: Should be
- "socionext,uniphier-pro4-usb3-regulator" - for Pro4 SoC
- "socionext,uniphier-pxs2-usb3-regulator" - for PXs2 SoC
- "socionext,uniphier-ld20-usb3-regulator" - for LD20 SoC
- "socionext,uniphier-pxs3-usb3-regulator" - for PXs3 SoC
- - reg: Specifies offset and length of the register set for the device.
- - clocks: A list of phandles to the clock gate for USB3 glue layer.
- According to the clock-names, appropriate clocks are required.
- - clock-names: Should contain
- "gio", "link" - for Pro4 SoC
- "link" - for others
- - resets: A list of phandles to the reset control for USB3 glue layer.
- According to the reset-names, appropriate resets are required.
- - reset-names: Should contain
- "gio", "link" - for Pro4 SoC
- "link" - for others
- See Documentation/devicetree/bindings/regulator/regulator.txt
- for more details about the regulator properties.
- Example:
- usb-glue@65b00000 {
- compatible = "socionext,uniphier-ld20-dwc3-glue",
- "simple-mfd";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x65b00000 0x400>;
- usb_vbus0: regulators@100 {
- compatible = "socionext,uniphier-ld20-usb3-regulator";
- reg = <0x100 0x10>;
- clock-names = "link";
- clocks = <&sys_clk 14>;
- reset-names = "link";
- resets = <&sys_rst 14>;
- };
- phy {
- ...
- phy-supply = <&usb_vbus0>;
- };
- ...
- };
|