8250.txt 2.5 KB

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  1. * UART (Universal Asynchronous Receiver/Transmitter)
  2. Required properties:
  3. - compatible : one of:
  4. - "ns8250"
  5. - "ns16450"
  6. - "ns16550a"
  7. - "ns16550"
  8. - "ns16750"
  9. - "ns16850"
  10. - For Tegra20, must contain "nvidia,tegra20-uart"
  11. - For other Tegra, must contain '"nvidia,<chip>-uart",
  12. "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
  13. tegra132, or tegra210.
  14. - "nxp,lpc3220-uart"
  15. - "ralink,rt2880-uart"
  16. - For MediaTek BTIF, must contain '"mediatek,<chip>-btif",
  17. "mediatek,mtk-btif"' where <chip> is mt7622, mt7623.
  18. - "altr,16550-FIFO32"
  19. - "altr,16550-FIFO64"
  20. - "altr,16550-FIFO128"
  21. - "fsl,16550-FIFO64"
  22. - "fsl,ns16550"
  23. - "ti,da830-uart"
  24. - "aspeed,ast2400-vuart"
  25. - "aspeed,ast2500-vuart"
  26. - "nuvoton,npcm750-uart"
  27. - "serial" if the port type is unknown.
  28. - reg : offset and length of the register set for the device.
  29. - interrupts : should contain uart interrupt.
  30. - clock-frequency : the input clock frequency for the UART
  31. or
  32. clocks phandle to refer to the clk used as per Documentation/devicetree
  33. /bindings/clock/clock-bindings.txt
  34. Optional properties:
  35. - current-speed : the current active speed of the UART.
  36. - reg-offset : offset to apply to the mapbase from the start of the registers.
  37. - reg-shift : quantity to shift the register offsets by.
  38. - reg-io-width : the size (in bytes) of the IO accesses that should be
  39. performed on the device. There are some systems that require 32-bit
  40. accesses to the UART (e.g. TI davinci).
  41. - used-by-rtas : set to indicate that the port is in use by the OpenFirmware
  42. RTAS and should not be registered.
  43. - no-loopback-test: set to indicate that the port does not implements loopback
  44. test mode
  45. - fifo-size: the fifo size of the UART.
  46. - auto-flow-control: one way to enable automatic flow control support. The
  47. driver is allowed to detect support for the capability even without this
  48. property.
  49. - tx-threshold: Specify the TX FIFO low water indication for parts with
  50. programmable TX FIFO thresholds.
  51. - resets : phandle + reset specifier pairs
  52. Note:
  53. * fsl,ns16550:
  54. ------------
  55. Freescale DUART is very similar to the PC16552D (and to a
  56. pair of NS16550A), albeit with some nonstandard behavior such as
  57. erratum A-004737 (relating to incorrect BRK handling).
  58. Represents a single port that is compatible with the DUART found
  59. on many Freescale chips (examples include mpc8349, mpc8548,
  60. mpc8641d, p4080 and ls2085a).
  61. Example:
  62. uart@80230000 {
  63. compatible = "ns8250";
  64. reg = <0x80230000 0x100>;
  65. clock-frequency = <3686400>;
  66. interrupts = <10>;
  67. reg-shift = <2>;
  68. };