xlnx,opb-uartlite.txt 693 B

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  1. Xilinx Axi Uartlite controller Device Tree Bindings
  2. ---------------------------------------------------------
  3. Required properties:
  4. - compatible : Can be either of
  5. "xlnx,xps-uartlite-1.00.a"
  6. "xlnx,opb-uartlite-1.00.b"
  7. - reg : Physical base address and size of the Axi Uartlite
  8. registers map.
  9. - interrupts : Should contain the UART controller interrupt.
  10. Optional properties:
  11. - port-number : Set Uart port number
  12. - clock-names : Should be "s_axi_aclk"
  13. - clocks : Input clock specifier. Refer to common clock bindings.
  14. Example:
  15. serial@800c0000 {
  16. compatible = "xlnx,xps-uartlite-1.00.a";
  17. reg = <0x0 0x800c0000 0x10000>;
  18. interrupts = <0x0 0x6e 0x1>;
  19. port-number = <0>;
  20. };