brcm,cygnus-audio.txt 1.9 KB

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  1. BROADCOM Cygnus Audio I2S/TDM/SPDIF controller
  2. Required properties:
  3. - compatible : "brcm,cygnus-audio"
  4. - #address-cells: 32bit valued, 1 cell.
  5. - #size-cells: 32bit valued, 0 cell.
  6. - reg : Should contain audio registers location and length
  7. - reg-names: names of the registers listed in "reg" property
  8. Valid names are "aud" and "i2s_in". "aud" contains a
  9. set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains
  10. a set of I2S_IN registers.
  11. - clocks: PLL and leaf clocks used by audio ports
  12. - assigned-clocks: PLL and leaf clocks
  13. - assigned-clock-parents: parent clocks of the assigned clocks
  14. (usually the PLL)
  15. - assigned-clock-rates: List of clock frequencies of the
  16. assigned clocks
  17. - clock-names: names of 3 leaf clocks used by audio ports
  18. Valid names are "ch0_audio", "ch1_audio", "ch2_audio"
  19. - interrupts: audio DMA interrupt number
  20. SSP Subnode properties:
  21. - reg: The index of ssp port interface to use
  22. Valid value are 0, 1, 2, or 3 (for spdif)
  23. Example:
  24. cygnus_audio: audio@180ae000 {
  25. compatible = "brcm,cygnus-audio";
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>;
  29. reg-names = "aud", "i2s_in";
  30. clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,
  31. <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,
  32. <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;
  33. assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
  34. <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,
  35. <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,
  36. <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;
  37. assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
  38. assigned-clock-rates = <1769470191>,
  39. <0>,
  40. <0>,
  41. <0>;
  42. clock-names = "ch0_audio", "ch1_audio", "ch2_audio";
  43. interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  44. ssp0: ssp_port@0 {
  45. reg = <0>;
  46. };
  47. ssp1: ssp_port@1 {
  48. reg = <1>;
  49. };
  50. ssp2: ssp_port@2 {
  51. reg = <2>;
  52. };
  53. spdif: spdif_port@3 {
  54. reg = <3>;
  55. };
  56. };