mt6797-afe-pcm.txt 1.2 KB

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  1. Mediatek AFE PCM controller for mt6797
  2. Required properties:
  3. - compatible = "mediatek,mt6797-audio";
  4. - reg: register location and size
  5. - interrupts: should contain AFE interrupt
  6. - power-domains: should define the power domain
  7. - clocks: Must contain an entry for each entry in clock-names
  8. - clock-names: should have these clock names:
  9. "infra_sys_audio_clk",
  10. "infra_sys_audio_26m",
  11. "mtkaif_26m_clk",
  12. "top_mux_audio",
  13. "top_mux_aud_intbus",
  14. "top_sys_pll3_d4",
  15. "top_sys_pll1_d4",
  16. "top_clk26m_clk";
  17. Example:
  18. afe: mt6797-afe-pcm@11220000 {
  19. compatible = "mediatek,mt6797-audio";
  20. reg = <0 0x11220000 0 0x1000>;
  21. interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_LOW>;
  22. power-domains = <&scpsys MT6797_POWER_DOMAIN_AUDIO>;
  23. clocks = <&infrasys CLK_INFRA_AUDIO>,
  24. <&infrasys CLK_INFRA_AUDIO_26M>,
  25. <&infrasys CLK_INFRA_AUDIO_26M_PAD_TOP>,
  26. <&topckgen CLK_TOP_MUX_AUDIO>,
  27. <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
  28. <&topckgen CLK_TOP_SYSPLL3_D4>,
  29. <&topckgen CLK_TOP_SYSPLL1_D4>,
  30. <&clk26m>;
  31. clock-names = "infra_sys_audio_clk",
  32. "infra_sys_audio_26m",
  33. "mtkaif_26m_clk",
  34. "top_mux_audio",
  35. "top_mux_aud_intbus",
  36. "top_sys_pll3_d4",
  37. "top_sys_pll1_d4",
  38. "top_clk26m_clk";
  39. };