sh-msiof.txt 3.6 KB

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  1. Renesas MSIOF spi controller
  2. Required properties:
  3. - compatible : "renesas,msiof-r8a7743" (RZ/G1M)
  4. "renesas,msiof-r8a7745" (RZ/G1E)
  5. "renesas,msiof-r8a7790" (R-Car H2)
  6. "renesas,msiof-r8a7791" (R-Car M2-W)
  7. "renesas,msiof-r8a7792" (R-Car V2H)
  8. "renesas,msiof-r8a7793" (R-Car M2-N)
  9. "renesas,msiof-r8a7794" (R-Car E2)
  10. "renesas,msiof-r8a7795" (R-Car H3)
  11. "renesas,msiof-r8a7796" (R-Car M3-W)
  12. "renesas,msiof-r8a77965" (R-Car M3-N)
  13. "renesas,msiof-sh73a0" (SH-Mobile AG5)
  14. "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
  15. "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device)
  16. "renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device)
  17. "renesas,sh-msiof" (deprecated)
  18. When compatible with the generic version, nodes
  19. must list the SoC-specific version corresponding
  20. to the platform first followed by the generic
  21. version.
  22. - reg : A list of offsets and lengths of the register sets for
  23. the device.
  24. If only one register set is present, it is to be used
  25. by both the CPU and the DMA engine.
  26. If two register sets are present, the first is to be
  27. used by the CPU, and the second is to be used by the
  28. DMA engine.
  29. - interrupts : Interrupt specifier
  30. - #address-cells : Must be <1>
  31. - #size-cells : Must be <0>
  32. Optional properties:
  33. - clocks : Must contain a reference to the functional clock.
  34. - num-cs : Total number of chip selects (default is 1).
  35. Up to 3 native chip selects are supported:
  36. 0: MSIOF_SYNC
  37. 1: MSIOF_SS1
  38. 2: MSIOF_SS2
  39. Hardware limitations related to chip selects:
  40. - Native chip selects are always deasserted in
  41. between transfers that are part of the same
  42. message. Use cs-gpios to work around this.
  43. - All slaves using native chip selects must use the
  44. same spi-cs-high configuration. Use cs-gpios to
  45. work around this.
  46. - When using GPIO chip selects, at least one native
  47. chip select must be left unused, as it will be
  48. driven anyway.
  49. - dmas : Must contain a list of two references to DMA
  50. specifiers, one for transmission, and one for
  51. reception.
  52. - dma-names : Must contain a list of two DMA names, "tx" and "rx".
  53. - spi-slave : Empty property indicating the SPI controller is used
  54. in slave mode.
  55. - renesas,dtdl : delay sync signal (setup) in transmit mode.
  56. Must contain one of the following values:
  57. 0 (no bit delay)
  58. 50 (0.5-clock-cycle delay)
  59. 100 (1-clock-cycle delay)
  60. 150 (1.5-clock-cycle delay)
  61. 200 (2-clock-cycle delay)
  62. - renesas,syncdl : delay sync signal (hold) in transmit mode.
  63. Must contain one of the following values:
  64. 0 (no bit delay)
  65. 50 (0.5-clock-cycle delay)
  66. 100 (1-clock-cycle delay)
  67. 150 (1.5-clock-cycle delay)
  68. 200 (2-clock-cycle delay)
  69. 300 (3-clock-cycle delay)
  70. Optional properties, deprecated for soctype-specific bindings:
  71. - renesas,tx-fifo-size : Overrides the default tx fifo size given in words
  72. (default is 64)
  73. - renesas,rx-fifo-size : Overrides the default rx fifo size given in words
  74. (default is 64)
  75. Pinctrl properties might be needed, too. See
  76. Documentation/devicetree/bindings/pinctrl/renesas,*.
  77. Example:
  78. msiof0: spi@e6e20000 {
  79. compatible = "renesas,msiof-r8a7791",
  80. "renesas,rcar-gen2-msiof";
  81. reg = <0 0xe6e20000 0 0x0064>;
  82. interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
  83. clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
  84. dmas = <&dmac0 0x51>, <&dmac0 0x52>;
  85. dma-names = "tx", "rx";
  86. #address-cells = <1>;
  87. #size-cells = <0>;
  88. };