hisilicon,histb-xhci.txt 1.4 KB

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  1. HiSilicon STB xHCI
  2. The device node for HiSilicon STB xHCI host controller
  3. Required properties:
  4. - compatible: should be "hisilicon,hi3798cv200-xhci"
  5. - reg: specifies physical base address and size of the registers
  6. - interrupts : interrupt used by the controller
  7. - clocks: a list of phandle + clock-specifier pairs, one for each
  8. entry in clock-names
  9. - clock-names: must contain
  10. "bus": for bus clock
  11. "utmi": for utmi clock
  12. "pipe": for pipe clock
  13. "suspend": for suspend clock
  14. - resets: a list of phandle and reset specifier pairs as listed in
  15. reset-names property.
  16. - reset-names: must contain
  17. "soft": for soft reset
  18. - phys: a list of phandle + phy specifier pairs
  19. - phy-names: must contain at least one of following:
  20. "inno": for inno phy
  21. "combo": for combo phy
  22. Optional properties:
  23. - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
  24. - usb3-lpm-capable: determines if platform is USB3 LPM capable
  25. - imod-interval-ns: default interrupt moderation interval is 40000ns
  26. Example:
  27. xhci0: xchi@f98a0000 {
  28. compatible = "hisilicon,hi3798cv200-xhci";
  29. reg = <0xf98a0000 0x10000>;
  30. interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  31. clocks = <&crg HISTB_USB3_BUS_CLK>,
  32. <&crg HISTB_USB3_UTMI_CLK>,
  33. <&crg HISTB_USB3_PIPE_CLK>,
  34. <&crg HISTB_USB3_SUSPEND_CLK>;
  35. clock-names = "bus", "utmi", "pipe", "suspend";
  36. resets = <&crg 0xb0 12>;
  37. reset-names = "soft";
  38. phys = <&usb2_phy1_port1 0>, <&combphy0 PHY_TYPE_USB3>;
  39. phy-names = "inno", "combo";
  40. };