ce4100.txt 1.4 KB

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  1. CE4100 Device Tree Bindings
  2. ---------------------------
  3. The CE4100 SoC uses for in core peripherals the following compatible
  4. format: <vendor>,<chip>-<device>.
  5. Many of the "generic" devices like HPET or IO APIC have the ce4100
  6. name in their compatible property because they first appeared in this
  7. SoC.
  8. The CPU nodes
  9. -------------
  10. cpus {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. cpu@0 {
  14. device_type = "cpu";
  15. compatible = "intel,ce4100";
  16. reg = <0x00>;
  17. };
  18. cpu@2 {
  19. device_type = "cpu";
  20. compatible = "intel,ce4100";
  21. reg = <0x02>;
  22. };
  23. };
  24. A "cpu" node describes one logical processor (hardware thread).
  25. Required properties:
  26. - device_type
  27. Device type, must be "cpu".
  28. - reg
  29. Local APIC ID, the unique number assigned to each processor by
  30. system hardware.
  31. The SoC node
  32. ------------
  33. This node describes the in-core peripherals. Required property:
  34. compatible = "intel,ce4100-cp";
  35. The PCI node
  36. ------------
  37. This node describes the PCI bus on the SoC. Its property should be
  38. compatible = "intel,ce4100-pci", "pci";
  39. If the OS is using the IO-APIC for interrupt routing then the reported
  40. interrupt numbers for devices is no longer true. In order to obtain the
  41. correct interrupt number, the child node which represents the device has
  42. to contain the interrupt property. Besides the interrupt property it has
  43. to contain at least the reg property containing the PCI bus address and
  44. compatible property according to "PCI Bus Binding Revision 2.1".