pmc.c 4.9 KB

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  1. /*
  2. * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/clk/at91_pmc.h>
  13. #include <linux/of.h>
  14. #include <linux/mfd/syscon.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regmap.h>
  17. #include <linux/syscore_ops.h>
  18. #include <asm/proc-fns.h>
  19. #include "pmc.h"
  20. #define PMC_MAX_IDS 128
  21. #define PMC_MAX_PCKS 8
  22. int of_at91_get_clk_range(struct device_node *np, const char *propname,
  23. struct clk_range *range)
  24. {
  25. u32 min, max;
  26. int ret;
  27. ret = of_property_read_u32_index(np, propname, 0, &min);
  28. if (ret)
  29. return ret;
  30. ret = of_property_read_u32_index(np, propname, 1, &max);
  31. if (ret)
  32. return ret;
  33. if (range) {
  34. range->min = min;
  35. range->max = max;
  36. }
  37. return 0;
  38. }
  39. EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
  40. #ifdef CONFIG_PM
  41. static struct regmap *pmcreg;
  42. static u8 registered_ids[PMC_MAX_IDS];
  43. static u8 registered_pcks[PMC_MAX_PCKS];
  44. static struct
  45. {
  46. u32 scsr;
  47. u32 pcsr0;
  48. u32 uckr;
  49. u32 mor;
  50. u32 mcfr;
  51. u32 pllar;
  52. u32 mckr;
  53. u32 usb;
  54. u32 imr;
  55. u32 pcsr1;
  56. u32 pcr[PMC_MAX_IDS];
  57. u32 audio_pll0;
  58. u32 audio_pll1;
  59. u32 pckr[PMC_MAX_PCKS];
  60. } pmc_cache;
  61. /*
  62. * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
  63. * without alteration in the table, and 0 is for unused clocks.
  64. */
  65. void pmc_register_id(u8 id)
  66. {
  67. int i;
  68. for (i = 0; i < PMC_MAX_IDS; i++) {
  69. if (registered_ids[i] == 0) {
  70. registered_ids[i] = id;
  71. break;
  72. }
  73. if (registered_ids[i] == id)
  74. break;
  75. }
  76. }
  77. /*
  78. * As Programmable Clock 0 is valid on AT91 chips, there is an offset
  79. * of 1 between the stored value and the real clock ID.
  80. */
  81. void pmc_register_pck(u8 pck)
  82. {
  83. int i;
  84. for (i = 0; i < PMC_MAX_PCKS; i++) {
  85. if (registered_pcks[i] == 0) {
  86. registered_pcks[i] = pck + 1;
  87. break;
  88. }
  89. if (registered_pcks[i] == (pck + 1))
  90. break;
  91. }
  92. }
  93. static int pmc_suspend(void)
  94. {
  95. int i;
  96. u8 num;
  97. regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
  98. regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
  99. regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
  100. regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
  101. regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);
  102. regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);
  103. regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);
  104. regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);
  105. regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);
  106. regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);
  107. for (i = 0; registered_ids[i]; i++) {
  108. regmap_write(pmcreg, AT91_PMC_PCR,
  109. (registered_ids[i] & AT91_PMC_PCR_PID_MASK));
  110. regmap_read(pmcreg, AT91_PMC_PCR,
  111. &pmc_cache.pcr[registered_ids[i]]);
  112. }
  113. for (i = 0; registered_pcks[i]; i++) {
  114. num = registered_pcks[i] - 1;
  115. regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
  116. }
  117. return 0;
  118. }
  119. static bool pmc_ready(unsigned int mask)
  120. {
  121. unsigned int status;
  122. regmap_read(pmcreg, AT91_PMC_SR, &status);
  123. return ((status & mask) == mask) ? 1 : 0;
  124. }
  125. static void pmc_resume(void)
  126. {
  127. int i;
  128. u8 num;
  129. u32 tmp;
  130. u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
  131. regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
  132. if (pmc_cache.mckr != tmp)
  133. pr_warn("MCKR was not configured properly by the firmware\n");
  134. regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);
  135. if (pmc_cache.pllar != tmp)
  136. pr_warn("PLLAR was not configured properly by the firmware\n");
  137. regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
  138. regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
  139. regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
  140. regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
  141. regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);
  142. regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);
  143. regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);
  144. regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);
  145. for (i = 0; registered_ids[i]; i++) {
  146. regmap_write(pmcreg, AT91_PMC_PCR,
  147. pmc_cache.pcr[registered_ids[i]] |
  148. AT91_PMC_PCR_CMD);
  149. }
  150. for (i = 0; registered_pcks[i]; i++) {
  151. num = registered_pcks[i] - 1;
  152. regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
  153. }
  154. if (pmc_cache.uckr & AT91_PMC_UPLLEN)
  155. mask |= AT91_PMC_LOCKU;
  156. while (!pmc_ready(mask))
  157. cpu_relax();
  158. }
  159. static struct syscore_ops pmc_syscore_ops = {
  160. .suspend = pmc_suspend,
  161. .resume = pmc_resume,
  162. };
  163. static const struct of_device_id sama5d2_pmc_dt_ids[] = {
  164. { .compatible = "atmel,sama5d2-pmc" },
  165. { /* sentinel */ }
  166. };
  167. static int __init pmc_register_ops(void)
  168. {
  169. struct device_node *np;
  170. np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
  171. pmcreg = syscon_node_to_regmap(np);
  172. if (IS_ERR(pmcreg))
  173. return PTR_ERR(pmcreg);
  174. register_syscore_ops(&pmc_syscore_ops);
  175. return 0;
  176. }
  177. /* This has to happen before arch_initcall because of the tcb_clksrc driver */
  178. postcore_initcall(pmc_register_ops);
  179. #endif