clk-exynos-clkout.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162
  1. /*
  2. * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  3. * Author: Tomasz Figa <t.figa@samsung.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * Clock driver for Exynos clock output
  10. */
  11. #include <linux/slab.h>
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/syscore_ops.h>
  17. #define EXYNOS_CLKOUT_NR_CLKS 1
  18. #define EXYNOS_CLKOUT_PARENTS 32
  19. #define EXYNOS_PMU_DEBUG_REG 0xa00
  20. #define EXYNOS_CLKOUT_DISABLE_SHIFT 0
  21. #define EXYNOS_CLKOUT_MUX_SHIFT 8
  22. #define EXYNOS4_CLKOUT_MUX_MASK 0xf
  23. #define EXYNOS5_CLKOUT_MUX_MASK 0x1f
  24. struct exynos_clkout {
  25. struct clk_gate gate;
  26. struct clk_mux mux;
  27. spinlock_t slock;
  28. void __iomem *reg;
  29. u32 pmu_debug_save;
  30. struct clk_hw_onecell_data data;
  31. };
  32. static struct exynos_clkout *clkout;
  33. static int exynos_clkout_suspend(void)
  34. {
  35. clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
  36. return 0;
  37. }
  38. static void exynos_clkout_resume(void)
  39. {
  40. writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
  41. }
  42. static struct syscore_ops exynos_clkout_syscore_ops = {
  43. .suspend = exynos_clkout_suspend,
  44. .resume = exynos_clkout_resume,
  45. };
  46. static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
  47. {
  48. const char *parent_names[EXYNOS_CLKOUT_PARENTS];
  49. struct clk *parents[EXYNOS_CLKOUT_PARENTS];
  50. int parent_count;
  51. int ret;
  52. int i;
  53. clkout = kzalloc(struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS),
  54. GFP_KERNEL);
  55. if (!clkout)
  56. return;
  57. spin_lock_init(&clkout->slock);
  58. parent_count = 0;
  59. for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
  60. char name[] = "clkoutXX";
  61. snprintf(name, sizeof(name), "clkout%d", i);
  62. parents[i] = of_clk_get_by_name(node, name);
  63. if (IS_ERR(parents[i])) {
  64. parent_names[i] = "none";
  65. continue;
  66. }
  67. parent_names[i] = __clk_get_name(parents[i]);
  68. parent_count = i + 1;
  69. }
  70. if (!parent_count)
  71. goto free_clkout;
  72. clkout->reg = of_iomap(node, 0);
  73. if (!clkout->reg)
  74. goto clks_put;
  75. clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
  76. clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
  77. clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
  78. clkout->gate.lock = &clkout->slock;
  79. clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
  80. clkout->mux.mask = mux_mask;
  81. clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
  82. clkout->mux.lock = &clkout->slock;
  83. clkout->data.hws[0] = clk_hw_register_composite(NULL, "clkout",
  84. parent_names, parent_count, &clkout->mux.hw,
  85. &clk_mux_ops, NULL, NULL, &clkout->gate.hw,
  86. &clk_gate_ops, CLK_SET_RATE_PARENT
  87. | CLK_SET_RATE_NO_REPARENT);
  88. if (IS_ERR(clkout->data.hws[0]))
  89. goto err_unmap;
  90. clkout->data.num = EXYNOS_CLKOUT_NR_CLKS;
  91. ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, &clkout->data);
  92. if (ret)
  93. goto err_clk_unreg;
  94. register_syscore_ops(&exynos_clkout_syscore_ops);
  95. return;
  96. err_clk_unreg:
  97. clk_hw_unregister(clkout->data.hws[0]);
  98. err_unmap:
  99. iounmap(clkout->reg);
  100. clks_put:
  101. for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
  102. if (!IS_ERR(parents[i]))
  103. clk_put(parents[i]);
  104. free_clkout:
  105. kfree(clkout);
  106. pr_err("%s: failed to register clkout clock\n", __func__);
  107. }
  108. /*
  109. * We use CLK_OF_DECLARE_DRIVER initialization method to avoid setting
  110. * the OF_POPULATED flag on the pmu device tree node, so later the
  111. * Exynos PMU platform device can be properly probed with PMU driver.
  112. */
  113. static void __init exynos4_clkout_init(struct device_node *node)
  114. {
  115. exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK);
  116. }
  117. CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu",
  118. exynos4_clkout_init);
  119. CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu",
  120. exynos4_clkout_init);
  121. CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu",
  122. exynos4_clkout_init);
  123. static void __init exynos5_clkout_init(struct device_node *node)
  124. {
  125. exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK);
  126. }
  127. CLK_OF_DECLARE_DRIVER(exynos5250_clkout, "samsung,exynos5250-pmu",
  128. exynos5_clkout_init);
  129. CLK_OF_DECLARE_DRIVER(exynos5410_clkout, "samsung,exynos5410-pmu",
  130. exynos5_clkout_init);
  131. CLK_OF_DECLARE_DRIVER(exynos5420_clkout, "samsung,exynos5420-pmu",
  132. exynos5_clkout_init);
  133. CLK_OF_DECLARE_DRIVER(exynos5433_clkout, "samsung,exynos5433-pmu",
  134. exynos5_clkout_init);